Design Of An Approximate Shift Multiplier Based On High Bit Detection Method

With the development of error-tolerant applications such as convolutional neural network,the rapidly growing network scale and layers lead to a significant increase in the power consumption and storage requirements of convolutional neural network accelerator.As an energy-saving scheme in error-tolerant applications,approximate calculation reduces the power consumption,delay and area of integrated circuits by sacrificing a certain data accuracy.Multiplication,as a basic operation,is widely used in circuit systems.Therefore,the design efficiency of multiplier will have a great impact on the overall performance of the system.In this thesis,a design scheme of approximate shift multiplier based on high bit detection method is proposed,and the high bit detection algorithm and hardware design strategy are proposed.The accuracy compensation strategy and low power consumption strategy are adopted to further improve the calculation accuracy of the approximate multiplier and reduce the calculation power consumption of the multiplier.The proposed approximate shift multiplier is simulated,compared and analyzed.The proposed approximate shift multiplier based on high bit detection method is applied in image processing and convolution neural network accelerator to prove its practicability and applicability.The approximate shift multiplier unit based on high bit detection method proposed in this paper has greatly improved the calculation accuracy and hardware performance.All design schemes are simulated under SMIC-40 nm process library.Compared with the accurate multiplier unit,our proposed multiplie reduces the power consumption by 51.13% and the area by 72.88%.Compared with the improved logarithmic multiplier ILM,the calculation accuracy of the subject scheme is improved by 39.45%.In the application of image processing,the peak signal-to-noise ratio of the image processed by our multiplier reaches 55.77 d B.Compared with the ALM and ILM multipliers,the image quality processed by the approximate shift multiplier is higher.In the verification environment of convolution neural network accelerator,the accurate multipliers in convolution array are replaced by the approximate multipliers.The overall power consumption of convolution calculation array is reduced by 43.42%,the area is reduced by 51.85%,and the recognition accuracy of convolution neural network is reduced by only 0.05%,which is within the acceptable range.In summary,the approximate shift multiplier unit based on high bit detection method proposed in this paper has obvious performance index optimization and accuracy index improvement,and the approximate multiplier can be applied in fault-tolerant system.