TWN Network Architecture And Circuit Design For Low Power Speech Keyword Recognition

Speech keyword recognition technology has been widely used in people’s daily life,among which the most widely used is in IOT devices such as mobile phones to facilitate human-computer interaction.This is why our speech keyword recognition system needs low power consumption,high precision and adapt to the requirements of complex environment.Based on the above requirements,this paper proposes a low-power speech keyword recognition accelerator based on optimized ternary weighted neural network(TWN).This paper mainly studies speech keyword recognition from the perspective of algorithm and hardware.In terms of algorithm,a high-precision and low storage ternary weight neural network speech keyword recognition system is designed for a variety of different noise scenes.The research contents of the algorithm include:1)this paper further optimizes the existing ternary weighted neural network algorithm,including proposing a neural network training scheme with controllable sparsity and a network training algorithm with convolution check weighting,which enables the neural network model to select its own appropriate sparsity according to the situation and compress the number of network weights to 67.6%before optimization;2)For the weight parameters of the network,the weight parameters are compressed according to the method of software and hardware collaborative design,which reduces the storage of weight parameters in hardware by 25.1%,and the recognition accuracy reaches 90.6%.In terms of hardware,the research contents include:1)using fewer processing elements(PE)and the array layout optimized for symmetric convolution,the data reuse rate is increased by 33.3%compared with the conventional PE array layout;2)A voice endpoint detection module for different environments is designed,which can adaptively identify the current voice environment and select appropriate computing strategies to reduce power consumption.The circuit design of this paper adopts TSMC 22nm ultra-low leakage technology,and the layout design area is 0.6mm~2.When the working frequency is 250k Hz,the minimum voltage test is carried out for the chip,the voltage of SRAM is 0.54V,and the voltage of logic circuit is 0.39V,the real-time processing of voice can be realized,and the power consumption under HVT process is about 3.8μW.