Research On 3D Array Reconfiguration Algorithm For Fault Area Exclusion

VLSI(Very Large Scale Integration)is an important development direction in today’s electronics technology,and its application areas involve computers,communications,medical,automotive,industrial control and many other fields.With the increasing integration of VLSI chips,the scale of chips is getting larger and larger,and the number of transistors on a single chip is also increasing,which leads to the increase of chip failure rate.Since chips are exposed to various risks of failure and malfunction in practical applications,it has become an important topic to study how to improve the fault-tolerance performance of chips.VLSI fault-tolerance technology can automatically detect faults and correct or bypass them when they occur,thus ensuring the proper operation of the chip.The degradation technique is currently the main technical means to guarantee fault tolerance,which reconstructs the sub-processor array from the mesh processor array containing the fault using as many fault-free processing units as possible,thus achieving fault tolerance performance.The fault-tolerant algorithm for two-dimensional switch architecture processor arrays has formed a more complete system,while the three-dimensional processor array fault-tolerance research is currently in the development stage,this paper is aimed at the switch architecture-based three-dimensional array degradation reconfiguration algorithm for research,the main research work is as follows:1.For the defects of existing algorithms,a heuristic algorithm based on fault-plane exclusion is proposed to improve the size of the constructed logical array,thus improving the utilization of fault-free units in the main array.The existing algorithm is a greedy planar routing based algorithm that backtracks when encountering a more fault-dense region,which raises the height of the previous logical cells,resulting in many unavailable fault-free cells between the two layers of the logical planes.When the fault density of the main array is too high,backtracking will occur frequently,which seriously reduces the reconfiguration efficiency of the existing algorithm.The algorithm proposed in this paper optimizes the existing algorithm by evaluating the fault characteristics of the physical planes,selecting the key planes that hinder the reconfiguration process to be excluded from the main array,and using the fault-free units on the fault plane to compensate for the adjacent faulted units,which reduces the frequency of backtracking of the existing algorithm and improves the reconfiguration performance of the algorithm for 3D processor arrays.The simulated experimental data show that the utilization rates of the existing algorithm and the proposed algorithm for fault-free units are 30.59%and 38.96%,respectively,on a 3D array with a random fault rate of 20%at the scale of 48×48×48,and the newly proposed algorithm achieves an improvement rate of 27.36%based on the existing algorithm.2.For the disadvantage that the strategy of excluding fault surfaces itself is accompanied by more additional losses,i.e.,the excluded fault surfaces have more fault-free units and cannot be utilized to construct subprocessor arrays,this paper also proposes a strategy of excluding cell nests.This strategy eliminates a smaller fault area,reduces the extra loss caused by the fault-plane elimination strategy,and is more flexible in the location of the selected fault area,which performs better than the fault-plane elimination strategy in the random fault distribution model.The experimental results show that the proposed algorithms improve the utilization of fault-free units in the processor array compared with existing algorithms.On a three-dimensional array of 64×64×64 size with 20%random fault rate,the utilization of fault-free cells by the existing algorithm,fault-plane based exclusion and cell nest based exclusion are 29.29%,34.24%and 44.53%,respectively,and the improvement rate of the existing algorithm is 16.87%and 52.03%,respectively.And the simulation experiments of cluster fault distribution show that the strategy based on fault-plane exclusion is more advantageous in performance than the strategy based on cell nest exclusion,for example,the harvesting rate of three algorithms on a 3D array with 32×32×32 scale,cluster fault size of 5×5×5,and the number of cluster faults of 16 is 16.44%,27.75%,and 20.87%,respectively,and the algorithm proposed in this paper has a The enhancement rates are 68.75%and 26.88%,respectively.