High Precision And Low Power Consumption Noise-shaping SAR ADC Design

Analog-to-digital converter(ADC)is a channel connecting analog domain and digital domain.Analog-to-digital conversion technology is widely used in image sensing,digital communication,measurement and signal processing.With the development of information technology and the popularity of mobile terminals,analogto-digital converters need to give consideration to high precision and low power consumption.It is difficult for traditional ADC to meet the requirements of high precision and low power consumption through a single architecture.In recent years,A new mixed ADC architecture,the Noise-shaping SAR ADC,combines the advantages of successive approximation register analog-to-digital converter(SAR ADC)and sigma-delta ADC architectures to achieve high precision and low power consumption at the same time.However,due to the advantages of the mixed architecture,the current design of Noise-shaping SAR ADC is generally difficult to achieve performance requirements such as high signal to noise distortion ratio(SNDR,> 90 d B),wide bandwidth and high precision.In order to solve the above problems,a SAR ADC with a resolution of 12 bit and a maximum sampling rate of 2 MSPS is designed in this thesis.Based on the SAR ADC,sigma-delta modulation is introduced to design a SAR ADC with a resolution of 16 bit.The hybrid architecture with the highest sampling rate of 2 MSPS has high precision and low power consumption in Noise-shaping SAR ADC.The SAR ADC circuit consists of bootstrapped switch,comparator,digital-to-analog converter(DAC)capacitor array and successive approximation register(SAR)logic circuit.Noise shaping method is added to the SAR ADC.The steps of noise shaping include sampling,shaping and summing of the residual voltage.The shaping step of the residual voltage is the key to shaping the accuracy of the noise-shaping SAR ADC.In this thesis,a second order integrating loop filter combined with a capacitive charge pump is proposed,which is a second order passive and lossless integrating loop filter,which compensates the integral loss in the traditional passive lossy integral and has good noise shaping effect.It compensates for signal loss and relaxes the design requirements for subsequent circuit designs.For different switching algorithms of DAC capacitor array,this thesis combines the inverted merged capacitor switching(IMCS)algorithm circuit with the loop filter in the noise shaping method.The IMCS algorithm has the advantages of low power consumption and can keep the common mode voltage of the top plate of DAC capacitor array.Finally,the Noise-shaping SAR ADC designed achieves high precision(SNDR,> 90 d B)and low power consumption(μW order).Based on 0.18μm 1P4 M CMOS technology,the overall layout area of Noiseshaping SAR ADC is 793 μm ×338 μm.Under the conditions of supply voltage of1.8 V,sampling clock frequency of 2 MHz and oversampling ratio of 8(bandwidth is125 k Hz),post-simulation of the whole circuit is carried out.The proposed passive lossless second-order integral is used to shape the noise.The simulation results show that noise-shaping SAR ADC has a good second-order noise shaping effect.A signal to noise and distortion ratio(SNDR)of 91.1 d B,an effective numbers of bits(ENOB)of14.84 bit,and an overall power consumption of 285 μW were achieved.