Low Power Design And Research Of Dual-mode Communication Chip Based On HPLC

At present,a new round of industrial convergence and technological revolution is emerging,the smart economy is flourishing,and the national grid is vigorously developing the "Ubiquitous Electricity Internet of Things" construction,in which smart meters adopt high-speed power line carrier and wireless channel(HPLC+HRF)dualmode communication technology to solve the data transmission accuracy and real-time problems arising from a single communication method.However,the dual-mode communication smart meters use real-time working mechanism,which makes the system power consumption increase significantly.In order to adapt to the trend of lowcarbon energy saving and improve energy utilisation,the system power consumption must be reduced,and the key to reduce the system power consumption is to solve the problem of low power consumption of dual-mode communication chip.This paper takes the HPLC communication part of the dual-mode communication chip as an example to illustrate the low-power design and implementation of the chip.The details of the study are as follows:1.The application requirements of low-power high-speed power line carrier communication and wireless communication dual-mode communication chips in smart meters and the development of low-power technology are investigated.Based on the performance index of the HPLC communication part of the dual-mode communication chip,the low-power design of the HPLC communication chip from the application layer to the physical layer is completed.The hardware and software co-processing design provides a mechanism to switch from receive mode or transmit mode to SLEEP mode or STOP mode,enabling low power consumption design at the application and network layers.The MAC(medium access control)layer,strongly coupled with the chip,uses beacon time slots to increase the network reference clock to achieve sleep mode and timed wake-up mechanism;the PHY(physical)layer divides the functional modules according to the working state of the transceiver data link path,and uses pipeline control to achieve gated clock insertion of each functional module to reduce power consumption of the signal transceiver process.2.In the front-end design of the chip,the whole chip is divided into four voltage domains to reduce the power loss caused by single voltage domain power supply.Combined with dynamic voltage regulation technology,a high-efficiency power converter circuit is used to achieve energy efficiency management of the power converter and a 10% reduction in redundant power consumption.Combined with frequency regulation technology,the entire chip uses four different frequency clock sources,each clock source and its crossover clock matching and switching to the system module to complete a reasonable division of high frequency and low frequency working circuits;the clock network of the entire chip is hierarchically gated clock configuration,inserting gated clock units at key nodes in the clock tree path,reducing the full clock path flip rate to achieve dynamic power consumption reduction,typical circuit Modem module overall dynamic power consumption is optimized by 6.2%.3,in the back-end physical design,through the optimization of wiring rules and clock units and the use of CCOPt(clock synchronization optimization)technology to optimize the clock tree,making the clock deviation optimization of 41%,the clock tree area optimization of 25%,the total power consumption optimization of 14.4%.In the layout and wiring phase,EDA tools were used to effectively plan device and module placement,reduce long alignments and enable chip layout design.Completed postsimulation verification of power consumption for different operating modes at two process angles,TT(1.10V/25℃)and ML(1.21V/125℃).4.The chip is implemented based on TSMC 40 nm LP eFlash process in QFN68 package.The chip power consumption test data shows that at room temperature of25 ℃ and 3.3 V,the chip power consumption is 0.09 W in receive mode and 0.13 W in transmit mode,meeting the expected power consumption targets.By comparing the simulation results of power consumption with the test results,the error between the two is less than 5%,and the low-power design implementation of this paper has certain engineering significance.