Design Of General Demodulator For Communication Integrated Measuring Instrument

With the continuous development of digital communication technology and semiconductor technology,the penetration rate of digital communication equipment is constantly increasing,and it is moving towards the direction of high speed,high order modulation and large bandwidth.How to accurately and efficiently test high-speed signals of various modulation formats is an urgent problem for current communication test instruments,and demodulation of high-speed multi-standard communication signals is one of the key technologies to solve this problem.Limited by the processing speed of the chip,the traditional serial demodulation method has been unable to meet the demodulation requirements of high-speed signals.Therefore,based on the idea of parallel demodulation,this project studies a high-speed universal demodulation algorithm that can support high bit rate,multiple symbol rates,and multiple modulation formats,The main research is summarized as follows:(1)Aiming at the problem of poor timing synchronization performance when the signal sampling rate is a non-integer multiple of the symbol rate,a high-speed resampling algorithm based on the Farrow structure is designed in this paper.The algorithm designs an 8-way parallel Farrow resampling structure,combined with the method of online calculation of time-varying interpolation coefficients,the sampling rate of high-speed signals can be adjusted to an integer multiple of the symbol rate,and the performance of timing synchronization can be improved.(2)Aiming at the problem that traditional serial filters cannot filter high-speed parallel signals,this paper designs a frequency domain filtering method based on parallel architecture.This method is based on the principle that time-domain convolution is equivalent to frequency-domain multiplication,converting time-domain signals to frequency-domain for filtering,avoids the convolution operation required for time-domain filtering,and improves the operation efficiency;and,the method According to the phase characteristics of the digital filter,the structure of the filter is simplified,the difficulty of design is reduced,the overhead of hardware resources is reduced,and the filtering of high-speed signals can be realized.(3)Aiming at the problem of out-of-synchronization of the sampling clock at the receiving end in the high-speed digital communication system,a parallel timing synchronization loop based on the O&M algorithm is designed in this paper.The loop maps the estimated value of the timing error into a rotation factor to correct the timing error in the frequency domain,which reduces the computational complexity.At the same time,pre-filtering is performed before the timing error estimation,which further improves the effect of timing error correction.FPGA-based algorithm tests show that this algorithm supports signals with a maximum symbol rate of 360 Msps and modulation formats of 16 APSK,32APSK,and 64 QAM,and the signal constellation diagram after timing error correction is more concentrated,and the maximum bit error performance loss is 2.03 dB,which is less than 2.2dB required by the index.