Verification Platform Design Of Layer Process Module In UVM＿based Display Processor

This paper is based on the UVM verification methodology to verify the RTL level of the Layer process module in the DPU,which is crucial in the DPU and is responsible for the interconversion of HDR and SDR image formats,and the interconversion of PQ HDR and HLG HDR.Based on these functions,the verification environment is built using the UVM verification methodology and the System Verilog verification language to simulate the real operating environment of the chip,and the components can be applied not only in this project,but also ported to other similar projects.The components involved in this paper are scoreboard,monitor,driver,sequence generator and interface,etc.The components are connected using TLM communication in UVM.After the verification environment was stabilized,the verification function points were extracted according to the algorithm and design documents,and test cases were written in System Verilog language to perform a large number of random tests.In the random test,we found that the reference model provided by the algorithm was wrong,and added an extreme constraint in the random test case,i.e.,the register values were all adjusted to the maximum or minimum values.After all the test cases were added,different random seeds were switched for a large number of regression tests,and no other design flaws were found during this process.Finally,the code coverage collection option was turned on to collect code coverage,and coverage groups were added to collect functional coverage.A coverage database was generated after each regression,and the VCS simulation tool was used to complete the merge action,and the coverage after each regression was merged together by the merge operation,and finally the functional coverage reached 100% and the code coverage reached 99.03%,which satisfied the acceptance index.The Layer process module can be designed correctly and functionally correct to provide the correct input for the back-end modules,and the correctness of this module provides a guarantee for the subsystem-level verification of the DPU.