Research And Design Of Low Power Consumption Technology For Multi-Bit Delta-Sigma Modulator

With the rapid development of digital signal processing(DSP)technology,as a bridge between analog signals and digital signals,analog-to-digital converters have attracted more and more attention from academia and industry.Delta-Sigma ADC trades for high precision by sacrificing working speed,which has lower requirements on technology and reduces the difficulty of circuit design,which is in line with the development trend of large-scale integrated circuits.Delta-Sigma modulator is a key part of Delta-Sigma ADC.How to reduce the power consumption of the Delta-Sigma modulator while obtaining higher precision is what this thesis will study.Thesis designs a low-power Delta-Sigma modulator.According to the required performance,a 3-order 3-bit discrete-time full feed-forward structure is selected.The modeling and simulation of the modulator is completed using MATLAB/SIMULINK simulation software,considering non-ideal factors,the SNR of 101 d B is obtained by simulation,so as to obtain the parameters required for the actual circuit design.Using the Cadence platform,using 180 nm CMOS technology and 3.3V voltage,the overall circuit design of the modulator is completed and the performance of each module is simulated to ensure that each The module realizes the required functions,and the self-adjusting switched capacitor integrator is designed to eliminate the offset voltage and reduce the1/f noise.The operational amplifier based on the inverter and the common-mode negative feedback of the switched capacitor are used to obtain a low-power operational amplifier.in the switched capacitor integrator.Although one-bit quantization is inherently linear,it is easy to cause overloading of the integrator and seriously degrade the performance of the modulator.This design uses three-bit quantization,uses DWA(Data Weighted Averaging)technology to eliminate the nonlinear influence of the feedback DAC,and uses passive summation The network replaces the conventional summing operational amplifier circuit and uses a Strong-Arm comparator with low dynamic power consumption as the comparator of the SAR ADC,thereby realizing the design of a 3-bit low-power quantizer.Transient simulation is carried out on the overall circuit of the modulator,the signal bandwidth is 2k Hz,the oversampling rate is 64,the input frequency is 593.75 Hz,and the amplitude is-2d BFS sine wave signal,the effective number of bits ENOB is 15 bits,and the SNR reaches 92 d B.The spurious dynamic range reaches105.9d B,and the power consumption is 0.732 m W under the voltage of 3.3V,which realizes the requirement of low power consumption.