Research And Design Of A High Performance Pipelined Analog-to-Digital Converter With Sample And Hold Amplifier

With the rapid development of digital processing technology,the analog-to-digital converter is used as a "bridge" between analog signals and digital signals.requirements.Pipeline ADCs are often used in the design of high-speed and high-precision ADCs because of their simple structure,easy reconfiguration,fast conversion rate,and high output accuracy.Therefore,it is of great significance to systematically study the key technologies of pipelined ADCs to achieve breakthroughs in high-speed and highprecision application scenarios.This thesis conducts an in-depth study on the design of a single-channel pipelined ADC,mainly researching and analyzing the error sources of the pipelined ADC and the key circuit modules and technologies that affect the performance of the ADC.The main work and innovations of this thesis are as follows.First,this thesis analyzes the working principle of pipeline ADC,divides the whole circuit into modules,and discusses the common circuit structure of each module.Then,this thesis conducts a detailed analysis of the error sources of each circuit module,and completes the construction of a behavioral model of the overall circuit.On this basis,it analyzes the influence of different module errors on the overall circuit performance,so as to guide the subsequent determination of the indicators of the overall circuit.and circuit design.Then this thesis studies the architecture of the pipelined ADC,and finally determines the circuit architecture as a sixstage pipeline structure with a sample-and-hold circuit.Wrong technology,the last level structure is 2-bit flash ADC.Especially,in terms of circuit design,this thesis establishes a circuit model to help analyze the frequency characteristics of the gain bootstrap op amp,and uses the conclusion of the model as a guide to design and complete the simulation verification of the op amps in SHA and MDAC.In addition,this thesis also designed and fully simulated the sampling switch,comparator,clock path and other modules to ensure that the circuit simulation performance under different process angles meets the design requirements.Based on the 40 nm CMOS process,this thesis designs and implements a pipelined ADC with 12-bit precision and 150 MS/s sampling rate.The overall area of the chip is 1900μm×1900μm.Under the condition of signal input and input signal bandwidth of 75 MHz,the overall power consumption of the chip is lower than 150 m W,and the overall circuit achieves high linearity.When the input signal frequency is 74 MHz,the SFDR of the overall circuit is 81.66 d B,and the ENOB is 10.86 bits.