Vertical Voltage Sustaining Technology And Experimental Research Of Kilovolt’s High Voltage Integrated Devices

The lateral double-diffused MOSFET(LDMOS)is equivalent to the series connection of the low-voltage MOSFET and voltage-sustaining layer,which has many advantages such as high speed,low loss,high withstand voltage,and easy integration,and is widely used in AC-DC converters,high-voltage gate drivers,LED drivers and other scenarios.The range of civil AC voltage in the world is 100 V～240 V,and the corresponding equivalent DC voltage range is 141 V～349 V.Considering the reflected voltage of the transformer in the circuit and the voltage spike generated by the inductor,the common high voltage LDMOS devices used in AC-DC converters need to have a breakdown voltage of 500 V to 900 V.For special applications such as unstable mains voltage in the Middle East or 380 V AC industrial power,higher-breakdown-voltage devices are required to ensure high circuit reliability.This study focuses on the realization of kilovolt-level high-voltage power integrated devices.Through theoretical analysis,it is found that the key to improving the longitudinal breakdown voltage of lateral devices is to widen the substrate depletion depth,and two technical paths are pointed out:increasing the substrate resistivity and adopting multi-junction depletion.Based on this,the design of kilovolt-level high-voltage integrated devices is optimized.The main innovation points of this thesis are as follows:1.A new process to introduce an N-type buried layer(NBL)in the substrate is proposed.N-type impurity ions are introduced into the substrate by etching the trench and implanting ions,and then diffuse and push together with the drift region to form NBL.The formation of NBL by this method avoids the high cost and process compatibility problems associated with epitaxy and does not introduce additional thermal processes.It is also compatible with the existing 700 V BCD(Bipolar-CMOS-DMOS,BCD)process of the partner company.2.A new structure is proposed to optimize the on-state breakdown voltage and off-state breakdown voltage of the device.When the device operates in the on state,a large number of electrons injected into the drift region break the original charge balance,and the high electric field peak near the drain makes the device’s on-state breakdown voltage decrease.In this thesis,we propose a split N-type top layer(N-top)and P-type buried layer(PBL)structure in the drift region and a continuous in the terminal region,which effectively reduces the high field near the drain and improves the on-state breakdown voltage of the device.This structure also optimizes the concave surface electric field in the drift region of the device when the device is operating in the off state,increasing the off-state breakdown voltage of the device.Based on the cooperative company’s 0.25μm BCD process platform,an NTTR LDMOS with split N and P islands was experimentally verified.The device has a breakdown voltage of 1002 V and a specific on-resistance of 123.57 mΩ·cm~2,which is 35%lower than the theoretical value of conventional Triple RESURF LDMOS.At the same time,a single-step experimental verification of NTTR LDMOS with NBL was performed.The N-type buried layer was successfully formed in the substrate through deep trench etching technology.The actual trench depth is 17.9μm and the radius of NBL is 13.3μm.