Research On Frequency Characteristics And Circuit Application Of New Vertical Structure MOS Devices For Small Size ICs

For a long time,the development of integrated circuits is inseparable from the reduction of transistor size and the improvement of chip integration.With the continuous advancement of process nodes,the scaling down rule has been difficult to meet the scaling requirements of integrated circuit units,and the integrated circuit industry has entered the post-Moore era.In the post-Moore era,the industry and academia have divided the development of Moore’s Law into three directions: "More Moore" represented by Fin FET and GAAFET,"More than Moore" represented by SIP,and "Beyond CMOS" represented by new material switching devices.The NanoDTMOS studied in this thesis is a new type of vertical channel structure based on SOI substrate,and the channel length is not limited by the lithography precision.This structure uses a different principle from Fin FET and GAAFET to suppress the DIBL effect and reduce device leakage current under short channel conditions.The drift region whose doping concentration is lower than the channel concentration is introduced,and the constant field of the channel region can be maintained by rationally adjusting the parameters of the drift region to change the withstand voltage of the device.The design of the lightly doped source region can prevent the punch-through of the channel region on the one hand,and can also eliminate the influence of parasitic BJT on the other hand.The use of SOI substrate can reduce the parasitic capacitance between the gate and the substrate,not only can improve the frequency characteristics of the device,but also can isolate the leakage current path between the device and the substrate,and has better electrical isolation capability.This thesis mainly does the following work on NanoDTMOS:1.The effects of the channel length,the vertical length of the drift region,the vertical length of the silicon dioxide trench,and the concentration of the drift region on the cutoff frequency of NanoDTMOS were explored,and the above effects were analyzed from the perspective of gate capacitance and device transconductance.2.The structural parameters of NanoDTMOS are optimized through the results of structural simulation and process simulation.The cut-off frequency of the optimized NanoDTMOS structure can reach 94.6GHz.Comparing NanoDTMOS and nanowall devices under the same channel length and drift region length,the cut-off frequency of the optimized NanoDTMOS is about 17% better than that of the nanowall device.3.Designed a ring oscillator IC,completed the corresponding layout design based on CMOS technology and nano-wall technology,and laid a good foundation for the future delay test of NanoDTMOS inverters.