Design And Verification Of Ethernet SoC Based On Cortex-M3

With the rapid development of Internet technology and the widespread use of personal computers,Ethernet card chips supporting PCIe have become indispensable.This thesis relies on the project "Ethernet Card Chip supporting PCIe".According to the requirements of the project indicators,the Ethernet chip should integrate Ethernet controller and PCIe controller,contain Ethernet PHY and PCIe PHY,support IEEE802.3protocol and GMII interface transmission,and contain PCIe gold finger.It can send and receive Ethernet packets correctly and has the functions of remote wake up and power consumption management.Based on the idea of hardware and software collaboration,complete overall architecture design of Ethernet SoC system,Cortex-M3 architecture design and Ethernet MAC controller design,and then uses Verilog language to implement the logic of MAC transaction layer,low-power module,bus matrix and memory module according to the designed architecture.The realization of low power through the software program control and hardware power management module support,does not need to change the structure of the media access controller,the logic is simple.In addition,the bus matrix is designed for Cortex-M3 peripherals and assigned addresses,and distributed arbitration with fixed priority can improve the system performance.In terms of software,based on the GCC toolchain,a power-on initialization program and four interrupt handling subroutines are written using the CMSIS toolkit.This way has the advantages of simple implementation and fast execution,and only after modifying the hardware address can realize the program reuse,and the portability is good.This thesis based on UVM verification methodology,VIP is used to build a system verification environment to verify the design of each hardware module.By checking the waveform of the signal and combining with the code disassembly file,the function of each module is confirmed to be correct.Due to the high complexity of system verification,only loopback verification is performed on the system.Data packets are successfully sent and received on the Ethernet side,and the data content is consistent.Finally,the correctness of SoC system functions is confirmed.