Ferroelectric Memory Fault Repair Circuit Design

Ferroelectric memory,a type of memory constructed from ferroelectric material,has been gradually gaining traction in the consumer market in recent years,offering faster read/write access and greater reliability than other memories,thus providing a broad scope of potential development.In order to improve the reliability and service life of ferroelectric memory,this thesis designs a fault repair circuit for ferroelectric memory.The core modules of this circuit are the fault test module,the redundancy analysis module,and the TCAM module,which together with the datapath module,the data selection module,and the ferroelectric memory main memory array and redundancy array form the ferroelectric memory fault repair circuit.In this thesis,we discuss the failure principle of ferroelectric memory from the physical level based on the structure of ferroelectric memory cells,and discuss the corresponding failure performance.After that,all the fault models of general memory are synthesized and all the possible faults of ferroelectric memory are abstractly modeled using fault primitives.For the established fault models,a dynamic March algorithm is proposed by comparing several classical March test algorithms,which can be adjusted according to the configuration information with certain flexibility and has a significant improvement of the coverage of dynamic faults.According to the dynamic March algorithm and a fault test circuit structure proposed in this thesis,a fault test circuit module is designed and a memory model with injected faults is established for simulation.The simulation results show that the dynamic March algorithm circuit designed in this thesis achieves the detection of faults.Starting from the built-in redundancy analysis technique,this thesis discusses the related techniques of redundancy analysis,the design and functional simulation of redundancy analysis circuits.Among them,the redundancy repair strategy is discussed first,and the problem is how to repair the circuit using redundant resources.In the design of redundant resource structure,the global redundant resource structure has obvious advantages.For the redundancy analysis algorithm,this thesis uses the improved basic standby pivot algorithm,discusses the algorithm repair principle,and gives an example.The BIRA module’s circuit is crafted using this algorithm,and the structural design and operational principle of the circuit are examined.The functional simulation of the circuit is then displayed.This thesis’ fault repair circuit is fashioned for ferroelectric memory,thus the structure of the ferroelectric main memory array serves as the foundation of the fault repair circuit.The main memory array combines the word line cut structure and the bit line cut structure to enhance the driving capability of the circuit.According to the address domain segment of the main memory array,the redundancy analysis circuit collects and analyzes the fault information.After the fault test and redundancy analysis are completed,the results are sent to the address remapping module,and when the subsequent data read/write operation is performed,the address remapping module will correspondingly have the faulty access address,thus performing redundancy replacement and realizing the fault repair of the ferroelectric memory.