Research On High Reliability GaN Power Device Gate Driver Circuit Technology

With the continuous development of GaN technology,a typical representative of the third generation semiconductor,compared with traditional Si devices,GaN devices have the advantages of lower on-resistance and no reverse recovery loss,so the power supply system with high power density and high reliability based on GaN power devices is gradually widely used in the market.Gate driver chip of power device is an important part of switching power supply conversion,but there are some reliability problems in the design process of enhanced GaN power device and its gate driver chip,Therefore,it is of great significance to design a high-reliability and high-performance GaN gate driver circuit for the technical development of GaN.This thesis analyzes the reliability problems and research status of the gate drive circuit of enhanced GaN power devices,and finds that the key reliability problems currently exist mainly include the severe negative voltage at the half-bridge power stage switching node during the dead time may lead to overshoot of the bootstrap capacitor and affect the reliability of the high-side power rail supply;the fast transient current and voltage changes generated by the power device in the occurrence of high-frequency switching transitions can affect the normal transmission of logic signals through parasitic parameter crosstalk affects the normal transmission of logic signals.Therefore,in this thesis,a highly reliable fully integrated GaN half-bridge gate driver chip is designed to address the above issues.Based on the existing enhanced Nchannel GaN device process,some sub-module structures of the gate driver system are optimized and designed.In order to improve the traditional high-side bootstrap power supply technology,an enhanced N-channel GaN switching transistor based on the output signal of the low-side driver stage controlled by the charge pump circuit is designed to realize the fast and reliable charging and discharging process of the bootstrap capacitor;Aiming at the d V/dt process of fast high voltage change at switching nodes and the problem of dead-time negative pressure at switching nodes,this thesis proposes a level shift circuit combining short pulse trigger with PWM control to enhance CMTI(Common-Mode Transient Immunity)performance and resist dead-time negative voltage.In addition,the undervoltage locking circuit designed in this thesis realizes the generation of undervoltage logic signals through current control and threshold voltage comparison,ensuring the reliability of signal transmission under the power rail;The designed driver stage circuit realizes low delay of the driving stage circuit and suppresses the parasitic crosstalk of the switching node through cascade of multi-stage bootstrap inverters and double N-transistor output.Based on the 0.8μm fully integrated GaN on SOI process,a highly reliable GaN halfbridge gate drive circuit and its key sub-modules are designed and simulated by using Cadence simulation software.Under the typical 48 V half-bridge input voltage and 1MHz switching frequency,the simulation results show that the signal transmission delay is about 18 ns,the delay matching is within 1ns,and the CMTI capability reaches 42V/ns.