Research And Design Of High Precision Low Power Successive Approximation Register ADC

Analog-to-Digital converter(ADC)as a bridge connecting analog signals and digital signals plays an important role in various electronic systems.Compared with several traditional ADCs,the Successive Approximation Register(SAR)ADC has the advantages of low power consumption and small area.With the continuous development of advanced integrated circuit technology,its sampling speed and accuracy have greater room for improvement,making SAR ADC widely studied in fields requiring medium-speed and medium-high precision.Especially in the field of precision data acquisition systems,instruments,and medical equipment,high-precision low-power SAR ADC is widely used.However,due to capacitor mismatch caused by manufacturing processes,the accuracy of ADC will be seriously limited.Therefore,it is of great significance to study the calibration technology to improve the accuracy of SAR ADC.In this thesis,an 18-bit high-precision low-power SAR ADC circuit has been designed based on the 0.35 μm CMOS process.The key sub-module circuits of the highprecision SAR ADC are deeply analyzed and studied.For the design of capacitive digitalto-analog converter(DAC),in order to meet the requirements of 18-bit quantization accuracy,based on the analysis of the principle of segmented capacitor array and redundancy technology,the "11+7" segmented structure is adopted to effectively save the area and power consumption of the DAC array.Three redundant capacitors are added to provide fault tolerance space for the comparison process of the SAR ADC.Combined with the self-calibration algorithm proposed in this thesis,the low-level capacitor at the negative end of the fully differential capacitor array is used as the calibration DAC,which makes the capacitor array DAC become a pseudo-differential structure.And a hybrid switch switching method combining monotonic switch and traditional switch is designed.In order to meet the accuracy and speed requirements of the comparator,a four-stage preamplifier and latch cascaded comparator is designed.The comparator circuit is simulated,the overall gain of the pre-amplifier is 67.7 d B,the bandwidth is 12.2 MHz,and the equivalent input noise of the comparator is 13.5 μV.To overcome the limitation of capacitor mismatch on the SAR ADC accuracy,a self-calibration analog calibration technology based on pseudo-differential structure is proposed,that is,using the low-level capacitance of the negative end of the DAC capacitor array with pseudo-differential structure to correct the mismatch of the high-level capacitance.It effectively saves chip area and power consumption without requiring additional capacitor arrays as calibration DACs compared with traditional self-calibration methods.The calibration algorithm model is established based on MATLAB tool,and the calibration algorithm is verified by behavioral-level simulation.Finally,the pre-simulation analysis,layout design and post-simulation analysis of the overall circuit of the 18-bit SAR ADC are carried out.The post-simulation results show that the effective number of bits of the ADC is 16.7 bits,the SFDR is 109.2 d B,the SNDR is 102.6 d B,the power consumption is 25 m W under typical process conditions.