Design Of Convlution Neural Network Accelerator For Abnormal Behavior Monitoring

With the popularization of video surveillance equipment and the need for security guards,the recognition and monitoring of human behaviors present in video has become a very important research topic.To address the problems of complex network structure and high computational complexity of existing human behavior recognition algorithms,this thesis focuses on the design of low-complexity behavior recognition algorithms and the design of a convolutional neural network accelerator for abnormal behavior monitoring.First,this thesis investigates the related work at home and abroad,compares the existing human behavior recognition algorithms,and proposes a low complexity human behavior recognition algorithm Light 3D based on this.This thesis uses a convolutional network to downsample the feature data,which,together with a smaller backbone network model,achieves high accuracy with low computational complexity,and lays the foundation for hardware implementation to reduce processing power and improve inference speed.Second,at the hardware level,this thesis analyzes the network structure of existing behavior recognition algorithms,summarizes the commonly used convolution operators,and designs a custom instruction set and hardware acceleration circuit for behavior recognition,which supports many common convolution operators in behavior recognition algorithms such as 1×3×3,1×1×3,and so on.The hardware circuit of the accelerator is based on an improved convolution operator.In this thesis,the accelerator hardware circuit is implemented based on an improved row-fixed data flow approach,which concentrates the local cache in PE into a global feature cache and a global weight cache,multiplexes the input,output and weight in space and time,and designs efficient computational paths according to the target operator,significantly improving the computational speed and computational efficiency.The accelerator designed in this thesis implements 2304 multipliers,which can complete up to 2304 multiplication and addition operations per clock cycle.8input channels parallelism,2 pixel parallelism and 16 output channels parallelism can be achieved in the 1 × 3 × 3 computation mode,and the maximum arithmetic power can reach 368.64 Gops at 160 MHz clock frequency.Finally,the designed algorithm and accelerator are tested and analyzed in this thesis.The proposed algorithm has 10.5M parameters and 2.6 Gops of computation,which is better than similar algorithms in terms of computation,number of parameters and recognition accuracy.In addition,the processing time of a single sample of the FPGA-based implementation of the accelerator combined with the proposed algorithm in this thesis is13.67 ms,the processing energy of a single sample is 0.76 J,the number of samples processed per second is 73.1,and the recognition accuracy on the UCF101 dataset is 95.78%,which is better than similar results in terms of real-time performance,energy efficiency,and recognition accuracy.