Design Of A High Speed Continuous-Time Sigma-Delta Modulator With RC-tuning

With the rapid development of 5G,global 5G equipment communication users have increased significantly,and operators have deployed a large number of new 5G base stations,and the number will continue to increase.As an important part of the radio frequency transceiver in the base station,Analog-to-Digital Converter is also in high demand.How to implement ADC with hundreds of megabytes of signal bandwidth and low noise density and power consumption is a big problem.Continuous time Sigma-Delta ADC is widely used in such high-speed scenarios because of its inherent anti-aliasing characteristic and good dynamic performance brought by noise shaping.Continuous time Sigma Delta modulator as the main component of continuous time Sigma Delta ADC has attracted much attention,and the suppression of various non-ideal factors of the modulator has also become a research hotspot.So how to realize high-speed continuous time Sigma-Delta modulator becomes very important and meaningful work.In this thesis,a continuous time Sigma Delta modulator is realized by using a topdown design method,in which an innovative RC-tuning circuit is used to tune the time constant error of the integrator.Firstly,the basic theory of Sigma-Delta modulator is provided.Starting from the basic sampling and quantization of ADC,the oversampling and noise shaping techniques are introduced.Then the high order modulator is analyzed theoretically,several typical high order loop filter structures are introduced,and the system architecture is selected.Then,the Delta-Sigma toolbox in MATLAB was used for behavior-level modeling,and key system parameters such as oversampling rate,order and quantization number were determined.In the behavior level model,SNR reaches 82.55 d B and SFDR reaches 94.36 d B at 100 MHz bandwidth.Then,the influence of various nonideal factors in the actual circuit,such as time constant error,limited gain and bandwidth of amplifier,DAC mismatch and clock jitter,etc.on the modulator is analyzed,and the compensation scheme is given,especially the RC-tuning circuit is added for the time constant error.Finally,according to the behavior level model and the scheme determined by the suppression of non-ideal factors,the actual top circuit and the specific circuit of each sub-module are obtained,including integrator,RC-tuning circuit,sub-ADC,feedback DAC,etc.The high speed continuous-time Sigma-Delta modulator implemented in this thesis adopts 40 nm CMOS technology and has an operating voltage of 1.2V.The simulation results show that when the signal bandwidth is 100 MHz,the effective resolution reach12.89 bits,the SNDR is 79.38 d B,the SFDR is 92.43 d B,the power consumption is72.67 m W,and the SNDR is 78.53 d B in the worst case.