Research And Design Of Key Technologies Of Multi-Stage Pipelined SAR ADC

With the continuous progress and development being made in signal chain technology,ADC(Analog-to-Digital Converter)has participated into every aspect of people’s life.Its importance has long been doubted.Because of its characteristics of many types and high complexity,ADC is often the center of gravity in integrated circuit design,of course,is also the difficulty in design.In recent years,with the development and popularization of communication technology and the proposal of 5G or even 6G technology,people’s requirements for the speed and accuracy of signal transmission and the convenience of equipment are greatly improved.Therefore,achieving higher performance but lower power consumption and smaller chip area has become a rising topic in the scientific research and industrial circles.Pipelined SAR ADC,as one of the mainstream architectures of low power and highspeed ADC,has not only the advantages of simple structure and low power consumption of SAR ADC but also high bandwidth of Pipelined ADC.It is a typical hybrid ADC architecture.This thesis optimizes and improves the architecture of the traditional twostage Pipelined SAR ADC.From the perspective of higher speed,a three-stage(4+4+6)Pipelined SAR ADC is designed and the system modeling are verified by MATLAB tool.Then using Cadence Virtuoso to design and simulate the actual circuit,and the performance of the circuit was optimized from the design of sampling circuit and residue amplifier.In this design,standard 28 nm CMOS technology is adopted,and 12 bits accuracy is achieved under the condition of supply voltage of 0.9V,full scale differential input voltage of 1.2Vpp and sampling frequency of 1 GHz.Total power consumption of the circuit is 11.2 m V.With a Nyquist input,the overall system indicators are as follows:SNR is 63.98 d B,SNDR is 63.27 d B,ENOB is 10.22 bits,and SFDR is 76.1 d B,and the Fo M of total circuit is 9.3 f J/conversion-step.With a low input frequency,the overall system indicators are as follows: SNR is 65.1 d B,SNDR is 64.2 d B,ENOB is 10.37 bits,and SFDR is 76.5 d B,and the Fo M of total circuit is 8.5 f J/conversion-step,respectively.