Design And Implementation Of Gigabit Ethernet Chip With PCIe Interface

In the era of Internet of Everything,network communication is an essential function of all electronic devices.Among all chips aiming at network transmission,gigabit ethernet chips with PCIe interfaces are widely used in aerospace,industrial control and other fields due to the ability for both ethernet transmission and high-speed data transmission with local devices.In order to meet the demand for localized network interface card chips in key areas,this thesis designs and implements a gigabit ethernet chip with PCIe interface.The gigabit ethernet chip with PCIe interface described in this thesis supports10/100/1000 Megabit Ethernet,as well as IEEE802.3 Ethernet protocol,IEEE802.1Q/p virtual local area network protocol and Wake-on-LAN function.It also supports PCIe1.1protocol,including power management and MSI capability.The thesis uses the ASIC design method to carry out the architecture design,key module design,system verification and system implementation of the chip,respectively,and describe each step in detail.In terms of architecture design,this thesis divides the chip into data path and control path,and designs two working modes:work mode and sleep mode.In the work mode,the network interface card chip transfers the Ethernet data between the PCIe system and the network interface card chip through DMA in the data path to transmit ethernet packet properly and can switch to the sleep mode under the control of the control path.In sleep mode,the network interface card chip uses software and hardware co-design method based on Cortex M3 CPU to turn off the on-chip clock through the control path,and waits to enter the work mode through wakeup frame or PCIe system wake up event.Subsequently,this thesis designs the key modules in the data path and control path in detail.A highly parallelized DMA for the PCIe bus and an on-chip buffer supporting Qo S functions are proposed in the data path,as well as a configuration path and a clock generation module are proposed in the control path.This thesis also integrates all modules of the network interface card chip and builds a verification platform based on UVM to verify the function of RTL-level circuits:constructs data receiving,data transmitting and data loopback sequence to verify the correctness of the data path;constructs working mode switching and receiving remote wake-up frame sequence to verify the correctness of the control path.Finally,this thesis describes the implementation steps of the network interface card chip based on 130nm process.Illustrating logic synthesis and sdc file,Floor Plan and clock tree synthesis,as well as the signoff work including static timing analysis and post-simulation specifically.The chip layout area is 14.44mm~2,and the reports of each step prove the correctness of the implementation.