Physical Unclonable Function And True Random Number Generator Design For IoT Security

With the rapid development of the Internet of Things(IoT)technology,ensuring the privacy of user information has become a critical issue.Traditional software protection methods are insufficient to meet the requirements of lightweight and low-power consumption for IoT device chips.This thesis investigated Physical Unclonable Functions(PUFs)and True Random Number Generators(TRNGs)from the perspectives of device chip supply and data security,in order to enhance the security of IoT devices.Firstly,taking the contact PUF as an example,this thesis proposed a more efficient post-processing method,SXOR,for contact PUF.SXOR can reduce the area of post-processing circuit and has practical value for implementing lightweight security modules for Internet of Things(IoT)devices.When the proposed post-processing circuit only accounts for 50.6%of the XOR area,the post-processing effects of SXOR and XOR are basically the same.The average Hamming weight of the PUF output bit sequence obtained by the proposed post-processing method is 0.499735,and the average Hamming weight obtained by the XOR-based post-processing method is 0.499999.In addition,this thesis successfully designs and implements a custom unit for contact PUF for automatic layout and wiring by combining the results of circuit simulation with the design method of full-custom digital unit.The thesis addresses the firmware protection issue in IoT devices by designing a lightweight firmware protection chip integrated with a PUF module.A contact PUF is used as the PUF implementation scheme and SXOR is employed as the PUF post-processing method.The chip provides identity authentication and data encryption/decryption functions,where the identity authentication is mainly achieved contact PUF and PUF is also involved in key generation for data encryption/decryption.The chip was implemented according to the standard digital IC design flow,using 65 nm process technology.The RTL(Register Transfer Level Design)code design of the chip is simulated,followed by logic synthesis and power timing analysis.Finally,physical implementation with back-end layout is performed.The chip has an area of 0.288 mm~2and consumes about 10 mW of power,with a core area of only 0.235 mm~2.A portable and lightweight true random number generator based on self-timing loop is designed and implemented on FPGA(Field Programmable Gate Array).The coherent sampling method with Gaussian jitter is simulated.It is found that when the frequency of the input signal and the sampling signal are close,the jitter of the input clock signal of the header sampling flip-flop is dominant in the generation of randomness.Then two theoretical analysis methods are proposed to strictly prove that the output of coherent sampling follows random uniform distribution under the premise that the jitter is Gaussian distribution.The sampling method uses coherent sampling true random number generator.The throughput rate of the post-processing module is 8 Mbps for 8 2-input LUTs,and the throughput rate of the post-processing module is 10 Mbps for 4 4-input LUTs.