Research On A Novel Longitudinal Structure MOS Integrated Circuit Process

In the development process of the integrated circuit industry,in order to maintain Moore’s Law,unit devices have evolved from bulk silicon MOSFETs to FINFETs and GAAFETs.The novel longitudinal structure MOS device described in this thesis mainly utilizes the high doping channel region and the low doping drift region in the drain region to form a unilateral abrupt junction,which can suppress the DIBL effect.The focus of this thesis is on the process implementation of the novel longitudinal structure,mainly discussing its related processes and process optimization.According to the structural characteristics of the novel longitudinal structure MOS device,the author of this thesis proposes the NMOS process flow,and carries out process simulation to ensure the realizability of its process.Then,the layout is drawn,and 0.35 um process is used.After the process is streamed,the transconductance and switching on voltage of the novel longitudinal structure MOS device are tested.It can be found that the test results are basically consistent with the results of process simulation.In order to explore a smaller channel length,the subsequent author has adopted a process plan of increasing annealing time to reduce the channel length.The annealing time was 30 seconds,40 seconds,and 50 seconds for slicing,and a 0.35 μ m process has been used for slicing.After slicing,testing has been conducted.Observing the test results of the annealed devices for 30 seconds and 40 seconds,it has been found that as the annealing time increased,the transconductance of the novel longitudinal structure MOS device increased,and the base breakdown voltage decreased,This phenomenon indicates that as the annealing time increases,the channel length decreases,while the device annealed for50 seconds exhibits resistance characteristics,indicating that the channel of the device annealed for 50 seconds has disappeared.When exploring smaller channel lengths,the author of this thesis has discovered the serious impact of technology on channel length.The author of this thesis has developed an NMOS channel length detection process,which can use electrical means to monitor the channel length of devices in real-time on the process line.The process simulation of the above process flow ensures the realizability of the process,and also verifies that the channel thickness is inversely proportional to the measured resistance.In order to develop a novel longitudinal structure MOS integrated circuit using Bi CMOS technology.In this thesis,the author takes NMOS as an example to develop the hybrid process flow and CMOS process flow compatible with NPN triode,and carries out process simulation and layout drawing to ensure the realizability of the process.Based on the structural characteristics of the novel longitudinal structure MOS device,the author of this thesis has optimized the structure of the novel longitudinal structure MOS device and applied for a patent.Compared with the novel longitudinal structure MOS device,the optimized novel longitudinal structure MOS device mainly improves the cutoff frequency.Through modeling and simulation,it can be found that the optimized novel longitudinal structure MOS device can increase the cutoff frequency by up to 68.72%.