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Research And Design Of Sigma Delta Modulator With 2-2 MASH Structure

Posted on:2024-01-31Degree:MasterType:Thesis
Country:ChinaCandidate:C C XuFull Text:PDF
GTID:2568307079966609Subject:Electronic information
Abstract/Summary:
In recent years,signal processing in the digital domain has become the mainstream of the times.Analog to digital converter(ADC)and digital to analog converter(DAC),as the only bridge connecting the analog world and the digital world,play a key role in signal processing.With the increasing requirements for ADC resolution in medical electronics,industrial control,and other fields,high-precision ADC gradually wins the favor of people.This thesis designs a 4-order discrete time Sigma-Delta modulator with a system architecture of 2-2 cascaded(Multi-st Age noise SHaping,MASH)structure.The first stage of the modulator uses a 4-bit quantizer,and the second stage uses a 2.5-bit quantizer,effectively reducing the impact of noise leakage in the front stage of the MASH structure.Data-Weighted Averaging(DWA)is used to deal with the element mismatch of multi bit DAC in the feedback loop of the first stage loop filter.Firstly,based on the MATLAB SIMULINK environment,this thesis conducts system level modeling of the modulator and analyzes the impact of circuit non ideal factors on the performance of the modulator.After that,guided by the modeling of the modulator system,the circuit design of the modulator is carried out.In the actual design,the first integrator of the first stage loop filter adopts the double sampling technology,which effectively improves the performance of the modulator without increasing the overall circuit power consumption.In addition,the modulator also uses chopper technology to reduce the flicker noise and DC offset voltage of the operational amplifier.The overall design is realized by 0.18μm standard CMOS process,and the working voltage is 3.3 V.The sampling frequency of the modulator is 2 MHz,and the oversampling rate is 128.The calculation results of Fast Fourier Transform(FFT)show that at the output data rate of 15.625 KSPS,the Signal-to-Noise Distortion Ratio(SNDR)of the modulator is 116 d B,the Spurious Free Dynamic Range(SFDR)is 118 d B,and the Effective Number Of Bits(ENOB)is about 19 bits,meeting the design specifications.
Keywords/Search Tags:Sigma-Delta modulator, MASH structure, Double sampling, DWA, Multi-bit quantization
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