Design Optimization And Implementation Of FFT Based On FPGA

In today’s era of high-speed communication,the widespread use of smart devices such as smartphones,self-driving cars,and Io T homes,has led to an explosive growth in the amount of data for digital audio,images,and videos.This has brought many challenges to digital signal processing technology.Fast Fourier Transform(FFT)is one of the basic algorithms in digital signal processing systems.As an important tool for spectrum analysis,it can be widely used in signal modulation and demodulation in digital communication,audio signals,and image and video signal processing.Due to the large amount of computation required by FFT algorithms in practical applications,high real-time requirements,and difficulty balancing dynamic range and computational accuracy,traditional software programming for FFT calculations cannot meet the needs of emerging scenarios today.Therefore,research and optimization of hardware implementation of FFT algorithms are of great significance.For audio and video fields,especially FFT calculations for high-resolution and high-frame-rate video data,this thesis proposes a pipeline FFT calculation circuit optimized based on FPGA.This design combines the radix-2~2SDF and SFF pipeline FFT structures while also using optimized half-precision floating-point numbers as data representation formats.Based on this hardware design scheme,this thesis builds a Matlab simulation model with bit-level precision.By running the simulation model,the differences in computational accuracy of several common FFT algorithms after hardware implementation are analyzed,proving the advantages of the radix-2~2algorithm in computational accuracy and computational complexity.This thesis also optimizes FPGA mapping of the hardware design scheme.According to the proportion of internal resources of FPGA,the structure of each level of SDF/SFF pipeline FFT is determined;according to the resource usage situation of shift registers and rotation factor memory,an optimization scheme for mapping them to the internal basic circuits of FPGA is formulated to minimize resource consumption.This thesis completes the hardware performance testing and functional verification work of this pipeline FFT circuit on XC7K325T FPGA.As demonstrated by the actual board results,the designed pipeline FFT circuit ultimately achieves complete consistency with the simulation results of the software model.The FFT operation in half-precision floating-point format can be achieved for sequence lengths ranging from64 to 1024,and the total resource usage is approximately 50%that of the Vivado xfft＿FP32 IP.The pipeline FFT designed in this thesis processes 1092 cycles at a processing time of 1024 points,with a maximum working frequency of 290 MHz.