Research And Design Of 5GHz Low Jitter Clock Generator

With the upgrading of semiconductor manufacturing technology,the characteristic size of integrated circuits is gradually reduced,the required clock signal rate in the circuit system is increasingly fast,phase-locked loop as an important part of the clock generation circuit,has been a research hot spot in recent years.This thesis studies the phase-locked loop to generate the clock signal for high-speed analog-to-digital converter circuit,the rate of the required sampling clock and jitter performance have high requirements.In this thesis,a linear loop model of phase-locked loop is established,and the working principle and circuit structure of each module are analyzed.Then the loop stability of the phase-locked loop is analyzed and the key loop parameters are calculated.The correlation between phase noise and clock jitter is briefly described.At the same time,the phase noise sources and corresponding transmission characteristics of each module are deduced and calculated.Next,the influence of sampling clock jitter on the performance of analog-to-digital converter is analyzed.The effect of flicker noise is more obvious due to the reduction of process size,which makes the performance of VCO worse.In addition,VCO needs a larger voltage control gain because the input frequency of high-speed ADC needs a wider adjustable range,which results in the VCO greatly limiting the phase noise performance of PLL.It is generally possible to choose to design a larger bandwidth of the phase-locked loop to suppress the near-end noise of the VCO,but this will inevitably increase the in-band noise introduced by the PFD and the charge pump.Therefore,an improved charge pump structure with several charge pump units working in parallel is designed,which can ensure a large dynamic range and effectively reduce the phase noise of the charge pump.At the same time,the combination of unit gain feedback and common mode feedback is used to reduce the dynamic current mismatch and the reference spur of the charge pump.In addition,this thesis uses a Top-R structure of VCO,and optimizes its variable capacitance and switched capacitance array to ensure a large voltage control gain and reduce the loss of the LC tank.After the specific circuit design is completed,the PLL layout design is completed according to the high-speed layout design method,then the parasitic parameters are extracted and verified by post-simulation.Finally,the phase noise and clock jitter are modeled and analyzed.Based on 28 nm CMOS process,an integer charge pump phase-locked loop with input frequency of 100 MHz～500 MHz and output frequency of 4 GHHz～6 GHz is designed.The simulation results show that when the operating frequency is 5GHz,the phase noise at 1MHz frequency offset is-116.66 d Bc/Hz,the phase noise at 10 MHz is-128.75 d Bc/Hz,the RMS jitter within the integration range of 10 KHz to 10 MHz is124.52 fs,the lock-in time of 240 ns and the overall power consumption is 6.25 m W.