Research On SOI LDMOS Device Used In Negative High Voltage Integrated Circuit

SOI high-voltage LDMOS devices are widely used in smart power integrated circuits such as consumer electronics,home appliances and industrial control due to their high integration,low cost,good isolation capability,and smaller parasitic effects.Negative high-voltage integrated circuits are used in some specific occasions,and SOI LDMOS plays a key role in negative high-voltage integrated circuits.Therefore,this thesis conducts research on SOI LDMOS devices used in negative high-voltage integrated circuits.The main work is as follows:First,the basic structure and working principle of SOI LDMOS devices are introduced,and then its electrical characteristics such as breakdown mechanism,device turn-on and working conditions,and on-resistance are introduced.Then,the back gate effect of the high voltage NLDMOS device in the negative high voltage integrated circuit is described,and the influence of the back gate effect on the breakdown characteristics of the NLDMOS is analyzed.Then,the dual conduction mode of the thick gate oxide SOI NLDMOS device is proposed and analyzed.Then three main layout structures of SOI LDMOS devices are introduced.Secondly,thick gate oxide SOI NLDMOS devices and thin gate oxide SOI PLDMOS devices for negative high voltage integrated circuits are designed and optimized.The breakdown voltage（BV）and specific on-resistance(R_on,sp)of the two devices were optimized by optimizing the length of the drift region and the dopant dose respectively;the metal source field plate,the metal drain field plate and the polysilicon gate field plate were introduced and their length were optimized to make the device obtain a more uniform surface electric field distribution and increase the BV of the device;then optimized the P-well and N-well doping doses respectively to modulate the threshold voltage(V_th)of thick gate oxide SOI NLDMOS devices and thin gate oxide SOI PLDMOS devices.Then the double conduction mode of thick gate oxide SOI NLDMOS device and the effect of back gate voltage on BV are researched by simulation.After optimization,the BV of the thick gate oxide SOI NLDMOS device reaches 312 V,the R_on,sp reaches 10.5 mΩ·cm²,and the V_th is 9 V;the BV of the thin gate oxide SOI PLDMOS device reaches-274 V,R_on,sp reaches 35.7 mΩ·cm²,and the V_th is-1 V.Finally,based on the simulation optimization results,the layout design and biasing of thick gate oxide SOI NLDMOS devices and thin gate oxide SOI PLDMOS devices were completed,and finally a total of 622 device layouts were drawn.After the tape-out experiment,the BV,Vth,and Ron,sp of the device were tested at the wafer level.The actual test results show that the BV of a typical tube of thick gate oxide SOI NLDMOS devices is 278 V,R_on,sp=7.6 mΩ·cm²,and V_th=9.5V;BV=-312 V,R_on,sp=20.9 mΩ·cm²,V_th=-0.9 V of a typical thin gate oxide SOI PLDMOS device.Finally,the negative high voltage driver chip is tested,and the test results show that the negative high voltage driver chip using the SOI LDMOS device designed in this paper can work as required.