Exploration And Experiment Of Cell Width Limit In Process For Integrated Submicron Super Junction

Power devices that transform and control electric energy are the core of electronic systems.They are considered as the breakthrough point of"Chinese chip."However,there is always a contradiction between breakdown voltage and specific on-resistance in power devices.The invention of super junction technology has greatly improved this problem.Super junction technology is widely used in power semiconductor devices.The super junction characteristics are related to the super junction cell width,smaller cell width leads to better characteristics.But cell width cannot be reduced indefinitely due to process limitations.In this thesis,we study the super junction when its cell width is reduced to the submicron level.Through theoretical analysis and simulation,we preliminarily obtained the theoretical cell width limit and the process cell width limit range of the submicron super junction.Guided by the theoretical research of the submicron super junction,we designed 500 V and 750 V integrated submicron super junction LDMOS and conducted chip experiments,and ultimately obtain better device performance.The main contributions of this project are as follows:Firstly,the concept of submicron super junction is proposed in this thesis.Submicron super junction refers to the super junction structure whose cell width is less than 1 micron.The key factors affecting the breakdown voltage and conduction mechanism of submicron super junction are analyzed.And the theoretical minimum cell size of submicron super junction is obtained.The design formula of submicron super junction is further modified on the basis of the traditional super junction design formula,and the relationship between breakdown voltage and specific on-resistance of submicron super junction is obtained by simulation.Then combined with the realization process of submicron super junction,the cell width limit of submicron super junction technology is obtained.Secondly,the submicron super junction is applied to 500 V LDMOS devices.The equivalent substrate and ideal bias conditions before submicron super junction injection are obtained by simulation.On this basis,the structure of integrated sub-micron super junction LDMOS device is simulated and optimized.Finally,the influence of submicron super junction on the switching characteristics of LDMOS devices is simulated and analyzed.Finally,experiments of integrated submicron super junction LDMOS devices are designed.The experiment was carried out based on a company’s 0.25μm 500 V～750 V BCD platform.Finally,the 500 V submicron super junction device was tested and the characteristics of V_B=622.6 V,R_on,sp=27.8 mΩ·cm² were obtained.The 750 V submicron super junction device was tested and showed the characteristics of V_B=836.2V,R_on,sp=72.6 mΩ·cm².Compared with Triple RESURF with the same bias,the theoretical limit of both specific on-resistance decreased by 62.2%and 56.7%,respectively.Finally,the HTRB experiment was carried out after the static characteristic test,and the failure reasons of HTRB were analyzed.