Design And Hardware Implementation Of Protocol Stack Based On RoCEv2 On Heterogeneous Computing Platform

With the continuous development of machine learning in the field of signal processing,many new application scenarios have emerged,such as smart antennas,adaptive modulation,intelligent anti-jamming,etc.The emergence of these new scenarios puts forward higher requirements for computing performance.Building a heterogeneous computing platform with multiple computing nodes which are FPGA chips or ZYNQ chips is an effective solution to improve computing power.The heterogeneous computing platform divides computing tasks into multiple subtasks and assigns them to different computing nodes according to the scheduling algorithm.Computing nodes need a highspeed and reliable transmission link to meet their own needs for reading and writing task data from other nodes.As a sub-content of a signal processing-oriented heterogeneous computing platform,this thesis aims to implement a communication link and meet the platform’s requirements for bandwidth,delay,scalability,and resource consumption.The main contents of the thesis are as follows:First,this thesis proposes a high-speed reliable transmission framework based on the Ro CEv2 protocol.This thesis first introduces the current mainstream data transmission scheme between computing nodes,and analyzes its shortcomings in terms of scalability,data delay and resource consumption,and finally proposes the communication link framework of this thesis.Secondly,this thesis implements the hardware of the Ro CEv2 protocol stack involved in the architecture.The thesis first uses the Vivado HLS tool to implement the transport layer and network layer of the protocol stack,and verifies its functionality through C-sim simulation and RTL simulation,then comprehensively optimizes it to meet the timing and resource occupation requirements,and finally implement the MAC layer and the physical layer of the protocol stack by the hardware description language and high-speed serial transceivers.Finally,this thesis uses Xilinx boards to build a system for testing between different computing nodes.In this thesis,the RDMA read and write operations between FPGAZYNQ and FPGA-FPGA nodes are tested separately,the payload of a single operation can reach 1024 bytes.Finally,the data throughput of the protocol stack under different size loads was tested,and the maximum can reach 9.34 Gbps after removing the header overhead.Compared with the existing framework,the high-speed reliable transmission framework proposed in this thesis adds a reliable transmission link between ZYNQ and FPGA chips commonly used in the field of signal processing,which has certain advantages in terms of data delay,scalability and implementation cost.It provides the underlying hardware foundation for the data interaction of computing tasks between computing nodes.