Mixed Mode Hardware Trojan Detection Based On Machine Learning

In recent years,the integrated circuit(IC)industry has become a cornerstone of the information society,and has been widely utilized in various fields such as industry,communication,medical,and other applications.However,with the globalization of IC design and manufacturing,the implantation of hardware trojans by third parties has become a significant threat to IC security.A hardware trojan can be implanted into an applicationspecific integrated circuit(ASIC)or field-programmable gate array(FPGA),and may lead to the leakage of important information,thereby seriously affecting the hardware security of modern intelligent systems.In addition,as the design level improves and the chip size increases,the proportion of hardware trojans in the circuit is decreasing,which has brought problems to traditional hardware trojan detection methods.To address these challenges,this dissertation analyzes hardware trojans during the design phase and proposes a netlist-level hardware trojan detection technology.This dissertation proposes a fine-grained hardware trojan detection method based on a hybrid feature set for the ASIC design process,with the aim of decreasing the time complexity of traditional detection methods for large-scale circuits.Firstly,from the perspective of optimizing the detection and analysis object,the principles and implementation methods of netlist circuit reconstruction are summarized,and a reconstruction small circuit technology is proposed and implemented,which reduces the detection scale and improves the detection efficiency.At the same time,in order to solve the accuracy problem of hardware trojan detection in large-scale circuits,a hybrid mode feature set including circuit structural features and signal features is further established,and the feature set is subject to importance analysis based on the random forest(RF)algorithm,removing the features that do not significantly contribute to the netlist classification.A machine learning classifier based on the categorical feature gradient boosting(Cat Boost)algorithm is established to achieve fine-grained detection of hardware trojans in netlists under the ASIC design process.The experimental results based on the Trust-hub trojan circuit library show that the proposed method achieves an average accuracy of 99.01%,a true positive rate of 90.84%,and an F1 comprehensive index of 88.93%.Furthermore,the method successfully detected100% of the trojans in the RS232＿T1300,RS232＿T1500,and RS232＿T1600 circuits,indicating its high effectiveness in identifying hardware trojans.Furthermore,this dissertation proposes a coarse-grain hardware trojan detection method based on netlist physical information for the FPGA field.The aim is to investigate the issue of hardware trojan detection in circuits of larger scale than the Trust-hub trojan circuit library,which has been a challenge for traditional detection methods.This dissertation takes the PUF security chip with a scale much larger than the traditional research circuit as the benchmark circuit and implants various types of hardware trojans into it,obtaining a trojan library more meaningful for large-scale circuit detection.Then,based on the principle that hardware trojans as additional redundant circuits will inevitably bring about a series of physical characteristic changes,such as structure,area,and power consumption,after being implanted in the circuit,a hybrid feature set based on the physical information of FPGA netlist modules is constructed.In order to solve the problem of imbalanced data where the number of pure circuit samples is much less than that of trojan circuit samples,different synthesis strategies are adopted to obtain more pure circuit samples,and the SMOTETomek algorithm is used to expand the data set,further improving the performance of the classifier.This method achieved 0 false negative results and 2 false positive results on the top-level modules of the circuit sample set based on the Vivado platform,and obtained an average accuracy of 93.24% and an F1 comprehensive index of 91.77%for the complete sample set,demonstrating the potential of the method to maintain design security in the FPGA design process.Regarding the performance optimization issues of the proposed detection methods,this dissertation conducts a multi-parameter analysis to identify and optimize various variables involved in the detection process.The aim is to improve the efficiency and accuracy of the detection methods for practical applications.Firstly,in the fine-grained hardware trojan detection technology,an improved method of reconstructing small circuits is proposed,and the advantages and disadvantages of different reconstruction methods are experimentally verified and summarized.Secondly,in the coarse-grained hardware trojan detection technology,based on the influence of clock frequency on circuit power consumption characteristics,the impact of different clock frequencies between 10 MHz and 500 MHz on the performance of the method is explored,and the positive impact of increasing the working clock frequency.Finally,a coarse-grained hardware trojan detection technology based on the Quartus platform is developed based on the differences in the underlying structure of different FPGA chips.The proposed coarse-grained hardware trojan detection technology based on the Quartus platform achieved a similar accuracy of94.44% as the Vivado platform,with all trojan circuits detected and only two false positive results,demonstrating its applicability to different FPGA platforms.