Study Of The New Homogenization Field SOI-LDMOS Device And Special Processes

SOI(Silicon on Insulator,SOI)material started to develop vigorously in the 1980 s,and it has entered the attention of scholars at home and abroad.SOI has many advantages such as low power consumption,latch-up resistance,radiation resistance and high integration.However,it is precisely because the dielectric layer blocks the substrate and the top silicon that the substrate cannot participate in the withstand voltage of the device.The voltage is completely determined by the thickness of the top silicon and the buried dielectric layer.Considering factors such as isolation and heat dissipation,the top silicon and the buried dielectric layer need to be as thin as possible.This has fallen into an irreversible contradiction in the application of ultra-high voltage.However,the mainstream SOI materials circulating in the market are still unable to mass-produce SOI integrated devices above 650 V.In this regard,many scholars at home and abroad have carried out research.One of the key directions is how to optimize the horizontal and vertical withstand voltage levels in SOI technology.The biggest limitation that has not been solved for many years is that many structures cannot be mass-produced on the process line.This article will focus on how to realize k V-level SOI integrated devices in the mainstream SOI materials in the current market,and discuss the basic mechanism of devices from the perspectives of horizontal withstand voltage technology and vertical withstand voltage technology.Carry out the research and development of special processes,propose new processes and test and verify them on the process line.First,a new shim SOI-LDMOS device structure is proposed,and the shimming technology withstand voltage layer of the new shim SOI-LDMOS device,the charge selfbalancing mechanism,and the periodic field modulation model that makes the transverse electric field uniform are introduced;based on the ENDIF theory Guided the longitudinal withstand voltage analysis of a new shim SOI-LDMOS device,which can enhance the longitudinal withstand voltage by reducing the normal electric flux and increasing the tangential electric flux path,and studied the effect of electrode depth on the device withstand voltage through simulation The new shim SOI-LDMOS device can obtain a device withstand voltage of no less than 1400 V on a material with a 13 μm top silicon buried layer of 4 μm,and a kilovolt-level device withstand voltage can be achieved in conventional SOI materials.Second,the concept of variable selectivity ratio is proposed.Under the protection of the new composite hard mask,the top silicon etching can be realized when the selectivity ratio is 35:1.When etching the buried oxide layer,the selectivity ratio is changed from 1:The 3-to-100:1 automatic conversion can complete the etching of the buried oxide layer under the condition of changing the selectivity ratio.Combined with the side wall protection technology,a new variable selectivity ratio etching technology has been developed for the first time.A buried oxide layer of about 1.5 μm was etched in the SOI material with a top silicon thickness of 15 μm,and the experimental verification was completed.Thirdly,a composite stress complementary technology is proposed.Due to the special structure of the dielectric buried layer between the top silicon and the substrate of SOI,the stress warpage in the initial state after the material is prepared is significantly larger than that of the bulk silicon,and the long-term thermal oxidation process of the deep trench isolation process of SOI further aggravates the The warping of the wafer also causes various abnormalities in the online process,and the multi-MIS structure of the new shim SOI-LDMOS device makes the warping problem more serious.Based on the different types and directions of stress application,it is proposed The concept of stress complementarity is understood,and the successfully developed composite stress complementarity technology solves the serious problem of silicon wafer warpage induced by deep trench sidewall oxidation in SOI materials,improves the output yield of SOI integrated devices,and is a new type of SOI-LDMOS The tape-out experiment of the device provides a guarantee of reliability.Second,the concept of variable selectivity ratio is proposed.Under the protection of the new composite hard mask,the top silicon etching can be realized when the selectivity ratio is 35:1.When etching the buried oxide layer,the selectivity ratio is changed from 1: The 3-to-100:1 automatic conversion can complete the etching of the buried oxide layer under the condition of changing the selectivity ratio.Combined with the side wall protection technology,a new variable selectivity ratio etching technology has been developed for the first time.A buried oxide layer of about1.5 μm was etched in the SOI material with a top silicon thickness of 15 μm,and the experimental verification was completed.