Design Of Highly Linear Power Amplifier Based On 5G RF Front-End

With the rapid development of the information society,it has become people’s vision to realize large data and high-speed transmission on mobile terminals,and the iteration of communication technology has attracted much attention.Compared with 4G,the fifth-generation mobile communication system(5G)has a very high peak rate,Advantages such as extremely low signal delay and support for more wireless device access.The innovation of wireless technology is inseparable from the development of radio frequency and microwave systems.The radio frequency front-end device is the physical cornerstone to achieve many goals of 5G,and the power amplifier greatly determines the system signal quality and work efficiency.Therefore,a 5G frequency band was developed.A power amplifier with high linearity,high efficiency and small size has high application value.This thesis designs a solution around linearity and efficiency,adopts InGaP/GaAs HBT technology,designs and tapes out a highly linear and small-sized power amplifier working in the 5G frequency band(3.3～3.6GHz),and the measured performance indicators meet the expected requirements.The main research results are:(1)A bias circuit with temperature compensation and linearization is proposed and realized on-chip.The HBT device with a vertical structure has a strong self-heating effect and diode rectification effect,which leads to a serious offset of the bias point.The bias circuit adopts the principle of temperature negative feedback and linearization compensation,which improves the linearity of the circuit and the overall performance.In actual measurement,when the temperature changes from-30°C to 90°C,the quiescent current changes to 3mA.(2)An output matching circuit with a harmonic suppression structure is proposed.Since the output port has the highest power and the distortion component interferes seriously,the harmonic power suppression can effectively improve the main frequency efficiency.At the same time,the resonant inductance in the circuit is set as an adjustable structure,which can Effectively avoid errors caused by process parameter changes.According to the actual measurement,when the output power is 28dBm,the second harmonic component is below-40dBc.(3)The power amplifier has a small size structure,the chip area is 0.83×1.7mm~2,and fully matched input and output.The small size can save manufacturing cost,and it is easy to integrate other devices into a complete RF front-end part.(4)Completed the simulation design of the power amplifier and the performance test after tape-out,and installed an ESD protection circuit on the contact port on the chip.The HBM capability is greater than 2KV.The final measured results are:the quiescent current is 170mA,the gain is 34～34.6dB,and the saturated output power reaches 33dBm.The output power at the 1dB gain compression point is 31.5dBm,the highest power added efficiency is 35%,and the adjacent channel power ratio is less than-35dBc at an output power of 28dBm.