Design Of Synchronization Module Combining Passive Precision Delay And Active Jitter Compensation

Current electronic devices require the cooperation of various types of modules to achieve the required functions of the system,so a precise synchronization system is required to maintain the timing synchronization of each sub-component of the system.Highly accurate programmable delay generators are used to generate the expected time interval between two consecutive pulses and are present as central components in many physical instruments,e.g.in Positron Emission Tomography(PET)systems,Solar Tower Atmospheric Cheren Cove Effect Experiment(STACEE)in gamma-ray astrophysics experiments,and in multipurpose conflict detector applications.In addition,a precision synchronization system is very beneficial for any timing experiments and tests.It has a wide range of applications in the fields of laser-matter interaction,inertial confinement fusion,radar,biomedical engineering,high-speed imaging,mass spectrometry,and spectroscopy.Although the existing commercial retarders such as DG645 and DG535 can achieve high-precision and low-jitter pulse output,such equipment are expensive.Since they are not specially designed for related application scenarios,these retarders are not suitable for mass spectrometers,spectrometers and Z-pinch etc.Moreover,the delay accuracy and delay range of commercial delayers are too large in these experimental applications and the number of channels is too small to meet the experimental needs and other deficiencies.If the number of devices is increased,since the commercial delay is an independent device,the total system volume is too large,which makes deployment much more difficult.Therefore,it is necessary to propose a convenient and universal delay generator architecture for scientific researchers to design special delay generators,which can achieve high precision,low jitter,and large-scale delay at the same time.In this thesis,a precise synchronization system structure design scheme combining a digital delay chip and an analog jitter compensation circuit is proposed.The relevant considerations are discussed in detail.The designed precision synchronization system is composed of a coarse delay module,a fine delay module,a control module and an analog circuit jitter compensation module.The coarse delay module is implemented by the FPGA using the digital delay method to count the system clock,the fine delay part is implemented by a high-precision digital delay chip,and the jitter compensation module is implemented by charging and discharging the capacitor with a high-precision constant current source.It satisfies the demand of the jitter compensation module for high-precision time measurement,realizes the modularization of the system,and reduces the development difficulty and complexity of the entire system.Due to the clock cycle of the digital circuit,the delay generator can achieve both the convenience of a digital delay chip and the low jitter characteristics of the output signal of the analog delay circuit,which not only meets the needs of the jitter compensation module for high-precision time measurement,but also reduces both development difficulty and complexity of the entire system.The experimental test of the delay generator shows that a delay range of 0-100μs,a delay accuracy of 10 ps and an output pulse jitter of less than 500 ps is realized.The delay range and delay precision of the delay generator designed with this architecture can be selected and adjusted by the specific designers according to their own needs.Due to its low output signal jitter and simple structure,designers can adjust the delay range and delay accuracy according to their needs.The proposed delay generator architecture shows strong practicability in many physical instruments.