Whole-chip Esd Protection Design For Low-voltage Cmos Technology

Electrostatic discharge(ESD)is a major factor affecting the reliability of semiconductor integrated circuits(ICs).As semiconductor process dimensions continue to shrink and gate oxide layers become thinner,the threat posed by ESD to semiconductor ICs and devices is increasing,presenting more challenging ESD protection design requirements.Traditional ESD protection circuits and devices are no longer sufficient to meet current protection requirements.In order to obtain more comprehensive ESD protection solutions,this paper investigates ESD solutions for low-voltage circuits based on basic CMOS processes.Optimization and improvement schemes are proposed for layout area,discharge path,and ESD and surge collaborative protection based on SCR(Silicon Controlled Rectifier)devices and circuits and power-ground clamp circuits.Firstly,this paper proposes a structurally optimized diode-triggered SCR device for low-voltage ESD protection.Although traditional SCR devices have high robustness,they suffer from the problem of high trigger voltage.To address this issue,a structure that introduces an additional diode in series as an auxiliary triggering circuit has been widely used but increases the overall device layout area.The proposed improved structure in this paper uses a diode series auxiliary branch that shares a cathode with the SCR path,reducing the layout area without compromising protection capability.Tests conducted using the 180nm IC manufacturing process show that the CCDTSCR has a trigger voltage of about 2.5V and a failure current of approximately 3.62A in TLP testing,equivalent to the DTSCR.In VFTLP testing,the CCDTSCR’s turn-on speed is optimized by 10%compared to the DTSCR.Secondly,this paper proposes an SCR design for I/O ESD protection.The discharge path from I/O to VSS is relatively long compared to I/O to VDD or VSS to I/O.Therefore,when a forward ESD event occurs from I/O to VSS,a higher voltage is generated at the I/O,resulting in greater electrical stress on internal circuits.The proposed structure in this paper uses an existing diode from I/O to VDD to construct an SCR device,with its cathode connected to VSS,achieving direct discharge from I/O to VSS and shortening the discharge path.Compared to traditional dual-diode structures,the proposed design offers better protection capability.Test results using the 180nm process show that the design has equivalent HBM voltages of 5850V and 5100V in PS and ND modes,respectively,higher than traditional dual-diode protection networks,and better voltage clamping effects than the other two traditional protection networks.Lastly,this paper proposes a low trigger voltage ESD/surge collaborative protection clamp circuit.Because surges have longer durations,traditional RC clamp circuits require very large time constants for the RC network,making them impossible to implement on-chip.Voltage-sensitive clamp circuits based on diodes can be used for ESD and surge protection simultaneously,but the diode series used in these circuits suffer from a balancing problem between static leakage and trigger voltage.The proposed circuit in this paper adds an RC detection network to the traditional diode-based voltage-sensitive clamp circuit,allowing the circuit to detect and protect against both ESD and surge events,and solve the problem of large static leakage in traditional clamp circuits.Test results using the 40nm process show that the clamp circuit has a failure current of about 4.9A and an HBM voltage of 7350V.The circuit offers good protection against ESD events,with reduced trigger voltage,leakage current,and layout area compared to traditional diode-triggered clamp circuits.In summary,this paper provides an in-depth analysis of ESD protection technology for low-voltage CMOS processes.By exploring the problems of existing technologies,this paper proposes a comprehensive set of optimization and improvement schemes from port protection devices to power-ground clamp circuits.The effectiveness of these schemes is verified through simulation and chip testing.