Research And Hardware Implementation Of Single Image Super-Resolution Reconstruction Algorithm Based On Deep Learning

In recent years,Super-Resolution Reconstruction(SRR)technology has been widely used in industrial production,medical image,aerial remote sensing and so on.The technology has low cost and high practical value.Aiming at the problems of large number of parameters and long reconstruction time of existing super-resolution reconstruction algorithms,this paper combines the multiple cascading mechanism and residual distillation module to design an improved algorithm based on information multi-distillation network,and the overall framework of the algorithm uses global residual and multiple cascade to integrate the shallow and deep features of the network,which increases the diversity of image features.The deep feature extraction layer is alternately placed with 4 residual distillation modules and 4 bottleneck layers.The residual distillation module promotes the network to extract deep features more flexibly and efficiently,and the channel spatial attention mechanism enhances the recognition ability of features,promotes the network to generate high-frequency detailed features,and improves the reconstruction quality of the algorithm.The bottleneck layer,on the other hand,greatly reduces network parameters.The algorithm is trained on the DIV2K dataset and tested on the Set5,Set14,BSD100,Urban100,and Manga 109 test sets.The experimental results show that the number of parameters of the algorithm proposed in this paper is 3.8×105,which is reduced to 1/3 of the original information multi-distillation network,and the network reconstruction accuracy is more competitive than the current mainstream lightweight SRR network.It is sufficient to prove that the proposed algorithm can reduce the amount of network parameters while maintaining good reconstruction accuracy.The algorithm in this paper uses ZYNQ to implement hardware deployment.INT8 quantization of the network is carried out in the way of quantization in training,and the hardware and software are divided according to the structure of the network.The PS terminal is mainly responsible for configuring the registers of the convolution accelerator and DMA as well as the overall process control.In order to reduce the cache pressure of the PL terminal,the PS terminal is used to process the channel fusion of the convolution accelerator and the image stitching part of sub-pixel convolution.The PL end is mainly responsible for the processing and calculation of the PS end commands and data,and gives the status signals under different operation modes for the PS end to query,and the corresponding convolutional layer,pooling layer and activation function of the network are implemented in the PL end.The convolution accelerator was encapsulated into IP and tested and verified on the andante level on ZYNQ platform with a clock frequency of 100MHz.Finally,the reconstruction time of the hardware network model was only 56.8ms and the power consumption was 3.7W.