Research And Implementation Of IQ Imbalance Compensation Algorithm For Millimeter Wave High Speed Communication System

Millimeter wave communication has become one of the key technologies for wireless transmission with larger bandwidth,higher speed and lower delay in the future.In addition,IQ modulation is the most widely used modulation mode in the communication system at present.The non-ideal characteristics of its RF components often make the amplitude and phase of the two transmitted signals inconsistent,which reduces the transmission quality of the system.In this thesis,the IQ imbalance estimation and compensation technology in the MMW high-speed communication scenario will be studied to ensure the accuracy of data transmission.In addition,hardware implementation will be achieved with Field Programmable Gate Array(FPGA)to achieve high throughput and low latency transmission characteristics in the baseband.The main research work of this thesis is as follows:(1)In order to achieve the characteristics of large bandwidth and high rate,the millimeter wave communication system architecture of single-carrier modulation and dual-polarized antenna was formulated,and the corresponding transmission frame structure and specific training sequence were designed.In addition,a set of mature timing synchronization scheme is developed to accurately extract the training sequence at the receiving end.Simulation analysis shows that this method has a good tip peak value.(2)Aiming at the IQ imbalance problem,a mathematical model in the time-frequency domain is established,and a multi-frame approach based on training sequence is proposed to estimate IQ imbalance in the frequency-domain.Through simulation analysis,the proposed method can improve the image rejection ratio from 20 d B before compensation to more than 40 d B after compensation under the condition that the amplitude difference is 1d B,the phase difference is 5°,the port isolation degree of polarized antenna and the signal-to-noise ratio are all 30 d B,and the bit error rate can be reduced to 0.01%-0.1%,showing good robustness.(3)In order to achieve the characteristics of low delay,the hardware implementation of synchronization and IQ imbalance modules is carried out by adopting parallel and pipeline-like architecture at the FPGA end,and some core computing units are optimized.IQ imbalance module adopts frequency-domain estimation time-domain equalization method,and the final data stream only needs 762 clock cycles from collection to IQ compensation.The delay at 300 MHz clock frequency is 2.54 us,and the actual effective throughput can reach 57.6Gbps.