Physical Design Based On 28 Nm Radiation Hardened Dsp Chip Sub-module

With the rapid development of our country’s aerospace field,the demand for high-performance and high-reliability radiation-resistant chips is increasing.When the size of the chip manufacturing process reaches the nanometer level,more and more units are integrated in a unit area,and the performance of the chip is greatly improved,but also the difficulty of physical design is suddenly increased.This paper takes the radiation-resistant DSP chip sub-module as the design object,adopts the 28 nm process,based on the Cadence platform,and uses the Innovus tool to complete the layout design from RTL to GDSII.The main work and innovations of this paper are as follows:(1)The influence of radiation effect on integrated circuits is studied,and the technology of anti-radiation hardening is systematically explained.2558 units have been hardened for single event effects,including combinational logic units,sequential logic units,and special units.And use the Liberate tool to characterize the parameters such as timing and power consumption of the reinforced anti-irradiation unit.By comparing with the general standard cell library,it is concluded that the reinforced unit is higher than the general library in terms of delay and power consumption.(2)Completed physical design related processes such as hard macro module layout,power planning,standard cell layout,clock tree synthesis,and signal routing.Combined with Star-RC and Prime Time tools,static timing analysis is performed on the chip after the physical design is completed,and the paths with timing violations are repaired to achieve timing closure standards.Physical verification of the layout,including design rule check,circuit rule check,and antenna effect check,etc.,and finally through physical verification.(3)The step-by-step clock tree synthesis method is adopted in the clock tree synthesis stage,which is different from the clock tree synthesis step recommended by Innovus.Using this method can reduce the insertion delay and clock skew of the clock tree to a certain extent,and the timing violation is also greatly reduced.In addition,in view of the influence of SET on the reset network,special processing of the reset network is carried out,so that the anti-SET performance can be further improved.This design uses the 28 nm radiation-resistant standard cell library to complete the physical design of the DSP chip sub-module.The module size is 24001500μm~2,the main frequency of the chip is 625 MHz,and the number of standard cells in the entire design is about 680,000.The timing is closed and the physical verification is passed.