Design Of Switched Capacitor Σ-Δ Modulator Based On The Integrator’s Error Control

The Σ-Δ modulator is the preferred solution for implementing an analog-to-digital converter in many different application scenarios.This thesis focuses on the study of circuit design method for the switched-capacitor Σ-Δ modulators.Typically,a hierarchical,top-down methodology is employed for the design of such complex circuits.Based on the system architecture and parameters,the design is first accomplished at the behavioral level,where the system performance requirements are translated into performance parameters for each constituted module circuit.Then,based on the performance specifications obtained for these module circuits,designs at the circuit-level are carried out.Due to the approximation nature of the behavioral models of the module circuits in the behavioral-level design,the accuracy of the design results cannot be guaranteed,which leads to iterations between the behavioral level and the circuit level.For Σ-Δ modulators,the design efficiency is typically low due to the time-consuming circuit-level simulation,making it a circuit with almost the highest design difficulty.This thesis first presents an efficient algorithm for the settling time-oriented design of switch-capacitor integrators.The algorithm can eliminate errors in the conventional approaches for the integrator design caused by approximations in the analytical behavioral models,and quickly accomplish the circuit design with a given settling time and accuracy.Building upon this algorithm,a Σ-Δ modulator design flow based on the fast look-up table behavioral simulation is proposed,which achieves the design of Σ-Δ modulators with the required SNR specification by continuously reducing the integration error of integrators in the modulator.Compared with the current hierarchical design methods,this approach allows for the consideration of all non-ideal factors in the real circuit,and has the advantage of having SPICE-level precision in the design of the integrator.Consequently,the accuracy of the subsequent modulator design can be well guaranteed.Furthermore,the fast simulation and high accuracy of the Σ-Δ modulator based on the lookup table model lead to lower computational costs for this design process.Therefore,the design efficiency is much higher than that of the commonly used hierarchical design method.The design flow is implemented in MATLAB combined with the HSPICE simulator.To verify the effectiveness of the methodology,a second-order one-bit CIFB and third-order one-bit CIFBΣ-Δ modulators are designed in TSMC 0.18μm CMOS technology.The design results are verified by full circuit simulation in Spectre.Finally,the layout of the second-order one-bit modulator is carried out and verified by the post-simulation.