Design And Verification Of Low Power Asynchronous Circuit Components

With the continuous expansion of the scale of on-chip circuits,the physical effects and timing problems faced in circuit design has become increasingly complex.The traditional digital circuit system is based on the synchronous circuit design method,and the power generated by the complex clock tree system accounts for an increasing proportion of the total power consumption of the chip.However,So C(System-on-Chip),No C(Network-on-Chip)and brain-like chips all have low power requirements,and in the brain-like chips,the working mode of the circuit is quite different from that of the synchronous circuit,while the asynchronous circuit based on the "event-driven" feature is more similar to the working mechanism of the brain and has the advantage of low power,so the asynchronous circuit has became a hot spot in the field of digital circuit research.This paper focuses on low power asynchronous circuit components,the design of asynchronous circuit components is completed,and the application methods of each component are described in detail.This paper first investigates the problems encountered by synchronous circuits in Very-Large-Scale Integration design and the advantages and design principles of asynchronous circuits.Based on FPGA,the asynchronous system using Click handshake circuit is implemented to verify its low power consumption characteristics.The components needed in the design of asynchronous circuits are designed.The main research contents and achievements of this paper are as follows:1.Based on the SMIC40 nm process,the Click handshake standard cell is designed,and its parameters are optimized to ensure that the logic function of the circuit is correct,and the generated fire pulse can drive the Flip-Flop,which can act as the local clock of the circuit in the asynchronous circuit and control the registers in the data path to update the data.2.Based on the idea of dynamic circuit,a high-performance Timing-Shift Flip-Flop(TSDFF)is proposed.The TSDFF removes Setup time,in the case of typical,the TSDFF clock-output delay speedup ratio reaches 188.6% compared to the DFF with the same drive capability in the standard cell library.In asynchronous system,TSDFF can effectively shorten the delay of data path and reduce the difficulty of timing analysis of asynchronous circuits.This paper also puts forward a method of using TSDFF to optimize the timing of digital circuits,make the circuit timing meet the signoff requirements as soon as possible.3.In order to solve the problem of timing matching in asynchronous circuits,a method of delay matching using programmable delay lines between handshake unit is proposed.The fixed time delay unit and the programmable delay line has been completed.The designer can configure the programmable delay line according to the delay length of the combinational logic in the data path to make the circuit timing meet the design requirements.4.A verification circuit was built with these designed components,and the functionality and performance of each component were verified.