Study On Device Performance Limit Of Graphene-like Monolayer Ⅲ-Ⅴ Transistors

The miniaturization of transistor size is the key to promoting the development of integrated circuits.However,when the length of the gate is reduced to less than 10 nm,the short channel effect becomes more and more significant,the ability of the gate to control the channel is greatly reduced,and the device performance is seriously degraded.Traditional silicon-based field effect transistors（FETs）is approached their physical limit,and Moore’s Law is at risk of failure.To effectively suppress the short channel effect,it is a typical solution to use emerging two-dimensional materials instead of the traditional bulk silicon materials as FET channels to improve the gate control ability of transistors,which is of great significance to the development of integrated circuits in the post-Moore era.As a member of the two-dimensional material family,two-dimensional III-V group materials not only have ultra-thin thickness and flat surfaces without dangling bonds but also have ultra-high carrier mobility and good stability,showing great potential to become the ideal channel materials for the next generation of nano-electronic devices.Based on the first-principles quantum transport simulation,the transport characteristics of metal-oxide-semiconductor field effect transistors（MOSFETs）based on graphene-like groupⅢ-V（planar structure Aluminum nitride（Al N）,gallium nitride（Ga N）,boron phosphide（BP）and boron arsenide（BAs））monolayer（ML）at sub-10nm scale are studied.The main performance parameters of the devices are calculated and compared with the requirements of the International Roadmap for Device and Systems（IRDS）.Then,the device performance is optimized by increasing the underlap（UL）and changing the doping concentration of the source/drain（N_s/N_d）.Finally,the length of the gate（L_g）is continuously reduced to explore their performance limits.Considering the lack of effective and controllable doping methods for ultra-thin two-dimensional materials in experiments,two-dimensional FETs usually require contact with metal electrodes for carrier injection.Therefore,the ML BP channel with excellent performance of both n-type and p-type devices is selected,and its electrical contact properties with various two-dimensional metal electrodes and the transport characteristics of ML BP Schottky barrier field effect transistors（SBFETs）with ML Zr₂NF₂ and 2H-VS₂ electrodes are studied.The results are as follows:（1）The performance of n-type MOSFETs with ML Al N and Ga N channels is better than their p-type counterparts.Compared with the reported n-type MOSFETs,n-type ML Al N（Ga N）MOSFET has the highest（second-highest）on-state current(I_on)at the sub-5 nm scale.It is found that when the L_g of n-type ML Al N（Ga N）MOSFET is reduced to 3（3）nm and 1（2）nm respectively,the device performance can still surpass the requirements of IRDS for low-power（LP）and high-performance（HP）devices.It is the first time to propel the L_g limit of LP/HP MOSFET to 3/1 nm.The research shows that ML Al N and Ga N are excellent candidate channels for the next generation of ultra-small-scale FETs.（2）Symmetrical n-and p-type performances are achieved for the ML BP and BAs MOSFETs,which is a hard-won advantage for complementary metal oxide semiconductor（CMOS）integrated circuits.The optimal n-/p-type ML BP and BAs MOSFETs can still meet the IRDS requirements for HP devices at L_g=3 and 5 nm,respectively.It is found that the optimal n-/p-type ML BP MOSFET possesses an ultra-high I_on of 2974/2937μA/μm at L_g=5 nm,exceeding most reported ML MOSFETs.The research suggests that ML BP and BAs are ideal channel materials for CMOS integrated circuits in the post-silicon era.（3）The contacts between ML BP and two-dimensional metals（Zr₂NF₂,Zr₂CF₂,Ti₂NF₂,Ti₂CF₂,1T-Ta S₂,2H-Ta S₂,1T-VS₂,and 2H-VS₂）are weak van der Waals（vd W）contacts with little hybridization.Fermi level pinning（FLP）is weak and there is no metal-induced gap state at the contact interface.It is found that ML BP SBFET with ML Zr₂NF₂（2H-VS₂）electrode is an n-（p-）type device with I_on,τ,and PDP of2959（2293）μA/μm,0.075（0.043）ps and 0.144（0.063）f J/μm,respectively,surpassing the requirements of IRDS for HP devices.The ideal electrodes of ML BP SBFET are proposed,which provide theoretical guidance for the development of high-performance devices in the post-silicon era.