Design And Implementation Of SM3 Hash Algorithm IP Core For IoT Security Chi

With the rapid development of computer technology and 5G technology,the Internet of Things(Io T)has penetrated into every aspect of social life.However,the rapid development of Io T also brings challenges to information security.Hash algorithms in cryptographic algorithms are one of the cores of information security.In many application scenarios such as bank IC cards,email transmission,and cloud data block links,hash algorithms play an important role.At the same time,cryptographic hash algorithms play a crucial role in the security protection process of Io T security chips.In this thesis,based on Io T security chips,a two-in-one SM3 hash algorithm IP core hardware implementation framework is proposed for the national commercial cryptographic algorithm SM3 hash algorithm.Verilog HDL hardware description language is used to model the above IP core framework,and it is simulated and deployed based on Io T security chips.The SM3 hash algorithm IP core designed in this thesis has been verified by simulation and logic synthesis,and the experimental results are consistent with the actual expectations.It has high performance throughput at low clock frequencies.The main research contents of this paper are as follows:1.Conducted in-depth research on the SM3 hash algorithm.Based on cryptography,the basic principles,algorithm flow,and operation steps of the SM3 hash algorithm were studied in depth,and the important applications of the SM3 hash algorithm in the field of information security were summarized.2.Implemented the design of the SM3 hash algorithm IP core based on Io T security chips.In order to meet the performance requirements of Io T security chips,a software and hardware co-design approach is adopted.A two-in-one implementation framework for the SM3 hash algorithm IP core hardware is designed,using loop unrolling and pipeline technology to improve the performance of the entire algorithm IP core.At the same time,the addition circuit was improved,optimizing the critical path of the compression iteration part to further improve the operation efficiency of the IP core.3.Conducted pre-simulation testing and FPGA board-level testing on the SM3 hash algorithm implementation solution proposed in this thesis.The analysis and comparison of the performance of this SM3 hash design solution with other implementation solutions show that this design solution meets the requirements of the project design chip,and all tests can pass.The SM3 hash algorithm IP core designed in this thesis is subjected to logic synthesis under SMIC 55nm process,and its area is 45786.756030 um~2.At a low clock frequency of125 MHz,the highest throughput of the IP core can reach 1939.4 Mbps.This performance indicator meets the performance requirements of the SM3 hash algorithm IP core in the 125MHz clock of Io T security chip So C architecture.