Noise Shaping SAR ADC Design

Analog to Digital Converter(ADC)is an indispensable module in digital signal processing,microcontrollers,some electronic instruments,and audio processing.The function of ADC is to convert continuous analog signals from nature,such as sound,temperature,light,etc.,into discrete digital signals for computer processing.With the rapid development of technology,the requirements for ADC in many electronic products have also increased,especially in terms of speed,accuracy,power consumption,and reliability.Although SAR ADC has the advantages of low power consumption,small area,and simple structure,it is difficult to achieve high-precision requirements at the same time.Sigma-Delta ADC is high-precision,but slow in speed and high in power consumption.Therefore,experts have proposed combining the two structures to obtain an ADC with dual advantages.In this paper,the noise shaping technology and oversampling technology in SAR ADC and Sigma Delta ADC are combined.The main work is as follows:1.Design a SAR ADC based on the SMIC 1P6 M 55nm process.In the overall design of this article,gate voltage bootstrap sampling,comparator,fully differential segmented capacitor array,and synchronous timing control are mainly used to obtain a 10 bit SAR ADC in the SAR ADC;The FFT result of the SAR ADC is:SNR=60.82 d B,SFDR=73.28 d B,and the effective bit is: ENOB=9.8bit.2.For the structure of NS SAR ADC,SIgma Delta modulator needs to be added to achieve noise shaping,so the dynamic comparator is changed to a four input dynamic comparator to sum the voltage margin,and the four input dynamic comparator is analyzed and improved.For the structure analysis of noise shaping,the structure finally adopted in this paper is a cascade feedforward structure,and finally the structure and oversampling technology are used to achieve noise shaping,You can obtain a 12 bit NS SAR ADC.This article is based on the SMIC 1P6 M 55nm process to conduct overall simulation verification on the finally designed NS SAR ADC.The final result is that the simulation verification is carried out at OSR=8 and a sampling rate of 1MHz/S when the power supply voltage is 1.2V.The FFT results of the NS SAR ADC designed in this article are: SNR=72.83 d B,SFDR=80.13 d B,ENOB=11.8bit..