Demosaic ASIC Design Based On Parallel Computing Architecture

With the continuous development of science and technology,people are increasingly demanding digital imaging systems such as cameras.One of the keys of digital imaging system is image signal processor,which largely determines the quality of the final image.The demosaic technology is an indispensable part of the image signal processor.It can interpolate the single color channel image collected by the color filter array to restore the three color channel image.If the demosaic algorithm is improperly implemented,there may be false color,zipper effect and moire lines distortion,which will make it more difficult for subsequent modules to process images.Academics in the field of demosaic algorithms focus on the quality of image recovery,but ignores the cost of hardware implementation.By contrast,the engineers place more emphasis on real-time hardware platforms.In the past,only low-cost,low-quality demosaic algorithms were selected,but with the advent of advanced semiconductor technology,more complex demosaic algorithms can now be implemented.Therefore,how to achieve high-quality,low-cost demosaic on hardware has become a common concern of industry and academia.This thesis is based on the actual project,puts forward an improved algorithm for the existing demosaic problem,and implements it under the relevant indicators to meet the hardware platform.The main research contents are as follows:(1)An improved demosaic algorithm based on gradient and homogeneity is presented.The algorithm introduces the theory of color difference consistency,direction gradient and homogeneity,making full use of the original information of the Bayer image.It not only can be implemented by hardware,but also can effectively suppress some distortion.The experimental comparison proves that the subjective image quality and objective evaluation index are better than some traditional methods.(2)A demosaic hardware system is designed.From the hardware implementation architecture to the interface definition of the sub-module,it is explained in detail.To reduce data row cache,a parallel computing architecture is proposed,which effectively reduces the area of demosaic hardware design.In addition,the design scheme of matrix window operation is highlighted and reused in many sub-modules.Finally,through the tool check,the hardware design code in this thesis is reliable and can be converted to a gate level netlist.(3)Based on the universal verification methodology,the design unit under test is tested in many aspects.First,according to the test point decomposition form,four test cases are designed,including algorithm function,register,performance pipelining,and outlier scenarios.Next,the module was tested and regressed for a long time and a number of rounds.All 53 test cases were passed without any errors.Finally,100%functional and assertion coverage and 97.51% code coverage were collected.The uncovered areas in code coverage are analyzed,and it is confirmed that the uncovered areas have no effect on the design logic.The above results show that the demosaic design in this dissertation is fully functional and can be implemented in hardware.