Research On The Soft-decision Based Decoding Algorithm Of Polar Codes And Its FPGA Design

In wireless communication systems,noise interference in the channel often leads to errors in the received information.In order to achieve reliable transmission of information,channel coding techniques are often used to enhance the anti-interference capability of information during transmission.As a channel coding technique that can reach the Shannon limit,polar codes have attracted much research from scholars and have been established as the coding scheme for the control channel in 5G enhanced mobile broadband scenarios under their excellent error correction performance.However,in practical application scenarios,the polarization effect of the channel with limited code length is limited,and there are always some intermediate channels that are not fully polarized,which can lead to degradation of the algorithm performance when these channels are used as carriers for information transmission.In order to promote the large-scale application of polar codes,it is necessary to improve the performance of existing decoding algorithms under finite code length and to design and implement efficient decoder architecture solutions.Based on the above needs,this thesis first investigates the basic theory of polar codes and its decoding algorithms.Then,to address the problem of poor performance of soft decision decoding algorithms,a class of improved soft decision cascaded decoding algorithms is proposed in this thesis.Finally,the hardware implementation of the proposed improved decoding algorithm is carried out in this thesis.The main research contents of this thesis and the research results obtained are as follows:(1)This thesis first conducts a detailed study of the soft decision-based belief propagation algorithm and the box-and-match algorithm in decoding algorithms.Then,for the poor performance of the belief propagation algorithm,by analyzing the codeword soft output information when the decoding of the belief propagation algorithm fails,this thesis finds that only a few information bits of the codeword soft output information is wrong,and the majority of information bits of the codeword soft output information is reliable.Based on this finding,this thesis considers some soft input and soft output decoding algorithms to cascade the soft output codewords when decoding the belief propagation algorithm fails.In order to reduce the decoding delay,this thesis proposes a soft decision cascade decoding algorithm by cascading the box-and-match decoding algorithm that can be decoded in parallel with the belief propagation algorithm.When the belief propagation algorithm fails to decode,the cascaded box-and-match algorithm can reprocess the passed soft output information to improve the algorithm’s overall performance.Finally,this thesis further applies the above cascade decoding method to the belief propagation list algorithm and proposes a list-based soft decision cascade decoding algorithm.The algorithm performs a bit-index permutation of the input vector so that all factor graphs can be decoded using the same standard factor graph,reducing the resource consumption of the hardware implementation.After simulating and comparing this algorithm with other algorithms,the simulation results show that the algorithm achieves a significant performance gain.(2)In terms of the hardware implementation of the decoder,this thesis first proposes the improved decoder’s overall architecture and elaborates the hardware implementation scheme of the essential sub-modules after a reasonable functional division of the decoder based on the principle of the proposed soft decision cascade decoding algorithm.Then,the hardware simulation tool is used to verify each decoder module’s functional implementation and simulation.The simulation waveform further verifies the correctness of the hardware implementation scheme.Finally,this thesis analyzes the resource usage and power consumption of the improved decoder and compares it with other cascaded decoders.The results show that the proposed decoder has advantages in logic and register resources.Meanwhile,the proposed decoder’s total power consumption is lower.