Research On Electrical Reliability Of 1200 V 4H-SiC MOSFET

Silicon carbide（SiC）,as an important wide bandgap semiconductor material,has excellent material performances.With the advantages of high insulation breakdown of electrical field,high saturated electron drift velocity,low dielectric constant and high thermal conductivity,SiC-based power devices can achieve lower on-resistance,higher switching frequency,lower cost of heat dissipation,greater ability of anti-irradiation and anti-electromagnetic pulse.Therefore,it is considered as an attractive alternative for silicon based power devices.As SiC-based power devices are mostly used in extreme situations such as strong electrical field,high temperature and large current density,the reliability under long-term operations is very important.Besides,high-density SiC/SiO₂ interface states are also one of the main reasons restricting their wider applications.Since 1200 V 4H-SiC metal oxide semiconductor field effect transistor（MOSFET）is one of the most promising SiC power devices in the market,it is very important to investigate its electrical reliability.Based on the technology computer aided design tools and the self-built testing platform,certain important electrical reliability issues of 1200 V 4H-SiC MOSFET are investigated in detail,such as the reliability of interface characteristics and gate oxide quality,the reliability under avalanche stress,and the reliability of body diode.Finally,the device design is optimized.The main content of this thesis is summarized as follows.（1）The distribution of SiC/SiO₂ interface defects is studied,and the density of the SiC/SiO₂ interface traps is monitored by the three-terminal charge pumping test.Firstly,various SiO₂ dielectric layer interface defects are classified,including their formation reasons,charge types,improving methods and impacts on the device threshold voltage,channel electron mobility and other electrical parameters.Then,the advantages and disadvantages of the current interfacial damage extraction method are analyzed,and the interface states distribution of the device under test is calculated by three-terminal charge pumping test.Finally,the calculated average density of interface defects is about 2.98×10¹¹ cm^-2e V^-1.（2）The transport and degradation mechanisms of gate leakage current(I_gss)of SiC MOSFET are revealed.Based on various current transport models,it is found that under low gate voltage,the leakage current is dominated by trap-assisted tunneling,which results in electron trapping into the oxide,increasing the electron tunneling barrier height,and decreasing I_gss.With the increase of the electric field,the Fowler-Nordheim tunneling current gradually dominates.The tunneling electrons generate the holes trapping in the oxide layer by the anode hole injection,reducing the electron barrier height and increasing I_gss.Finally,it is found that the defect energy level concentrates from 0.25 e V to 0.37 e V,so the appropriate passivation process is the key to reduce I_gss and improve the quality of oxide layer.In addition,the degradation of I_gss under negative gate voltage are analyzed.The difference in anode hole injection results from the different barrier height of conduction band between Polysilicon（Poly Si）and SiC relative to SiO₂.（3）The degradation mechanism of planar SiC MOSFET under repeated unclamped induction switching（UIS）tests is studied.Firstly,by using the UIS experimental platform and Sentaurus software,the degradation behavior of static and dynamic parameters after repeated UIS test is deeply analyzed.Then,the data of I_gss are fitted based on the Fowler-Nordheim tunneling,and it is found that the barrier height of SiC/SiO₂ decreases gradually from 2.52 e V to 2.06 e V with the increase of UIS test cycles.Finally,the current transport process in oxide of SiC MOSFET after repeated UIS test is explained.The results show that under the repeated avalanche stress,a large amount of positive charge is injected into the gate oxide layer on the junction field-effect transistor,affecting the electric field distribution and the thickness of the depletion region,leading to the electrical parameter degradation of the device,such as on-resistance,drain-source leakage current and capacitance characteristics.In addition,the accumulation of positive charge in the oxide increases the electron tunneling current through the gate dielectric layer.The results provide a theoretical basis and reference significance for improving the UIS performance of SiC MOSFET.（4）A planar SiC MOSFET（PS-MOS）integrated with freewheel diode is proposed.The device has the split gate,where the gate Poly Siis divided into the left and the right parts by the source Poly Si,and an additional P-shield region is added to the bottom.The source Poly Siis connected to the P-shield region through the freewheel oxide.This structure makes the internal freewheel diode can replace the body diode under reverse bias,suppressing the bipolar degradation effect caused by the combination of electron and hole pairs in the traditional SiC MOSFET,and the on-state voltage drop of the freewheel diode is smaller than that of the body diode,helping to reduce the power consumption of the circuit.In addition,the split gate replacing the traditional whole gate improves the capacitance characteristics and Miller’s effect of the device,helping to reduce the switching loss and switching time.The P-shield added at the bottom is designed with special concentration to protect the bottom oxide layer without affecting the conduction characteristics,which can also be the channel of the freewheel diode.When PS-MOS is switched back to the on-state,the charge stored in the P-shield can be recovered immediately by the source Poly Si.