Research And Design Of Low-Power Read/Write Circuits For STT-MRAM

Spin Transfer Torque Magmetic Random Access Memory(STT-MRAM),an emerging memory,is one of the strong candidates for next-generation on-chip cache and general-purpose memory due to its non-volatility,zero static power consumption,near-infinite number of erasable writes,high integration and compatibility with CMOS processes.This dissertation explores and investigates the read-write power consumption and reliability of STT-MRAM from the read-write circuit level and memory architecture level.Firstly,a sense amplifier(SA)operating near the threshold voltage was designed to greatly reduce the reading consumption and eliminate the effect of leakage current.Then,for the write circuit,a double-ended superposition anti-noise resistance monitoring write termination scheme is proposed,which has a great improvement in the sensing margin,bit error rate,retention yield,termination yield,back hopping yield,write done signal delay,energy-delay-product.Then,based on the current perpendicular magnetic anisotropy(PMA)magnetic tunnel junction(MTJ)model driven by spin transfer torque(STT)and CMOS model of 65 nm process,the performance of the designed read/write circuit on memory arrays and on-chip caches is evaluated.Finally,in order to explore the application of low-power read and write circuits in logic-in-memory,a low-power logic-in-memory computing architecture based on spin logic devices is proposed.The major contributions of this dissertation can be summarized as follows:(1)Leakage-Current-Canceling Current-Sampling Sense Amplifier for Deep Submicrometer STT-RAM.In the design of nonvolatile memory(NVM),the sense amplifier(SA)contributes a major part of the power consumption due to high-frequency read operations.We propose a leakage-current-canceling current-sampling sense amplifier(LCCS-SA)for the suppression of the read power consumption by operating in near-threshold region.The proposed LCCS-SA adopts the technology of offset cancellation and singleended differential circuit structure to compensate the effect of the leakage current.The bit-line(BL)leakage-induced read failure is effectively suppressed in near-threshold region.Monte Carlo simulation demonstrates that the proposed LCCS-SA can operate at a supply voltage of 0.4 V and greatly reduces the power consumption per bit read.(2)Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM.Although resistance monitoring write termination(RM-WT)scheme for STT-MRAM can reduce the write energy,the degradation of read margin due to low tunnel magnetoresistance ratio(TMR)and intrusion of noise with process variation still seriously deteriorates the stability of the WT operation.In this paper,a double-ended superposition anti-noise write termination(DSA-WT)scheme is proposed and implemented,in which the voltage changes on both BL and SL can be superimposed to boost sensing margin(SM).Schmitt trigger(ST)is adopted to take the place of the inverter(INV)in the traditional WT scheme,which is demonstrated to be helpful for stability improvement.Based on 65-nm CMOS technology,the proposed DSA-WT scheme has significantly improved sensing margin,read bit-error-rate,write done delay and energy-delay-product under various PVT conditions.(3)A Low-Power Logic-In-Memory Computing Architecture Based on Spin Logic Device.A low-power logic-in-memory computing architecture is proposed based on a programmable spin logic device with an electronically controlled magnetization switch.Based on Pt/Co/Al Ox structure,the spin device can realize field-free perpendicular magnetization switching and controllable switching polarity by utilizing the asymmetric bilateral gate voltagesΔV_G.Furthermore,together with the ability of voltage-controlled magnetic anisotropy(VCMA)effect to regulate the critical SOT current,the spin logic device exhibits more diverse programmability.There are five Boolean functions as well as the half adder function can be experimentally demonstrated with the fabricated spin logic device.The logic-in-memory computing architecture is implemented by combining low-power read/write circuit with spin logic devices.