| In recent years,with the rapid development and wide application of indoor positioning technology,the demand for achieving high-precision,low-power,low-cost indoor positioning is growing.Especially in the era of the Internet of Things,more and more application scenarios need to accurately obtain users’ indoor location information in real time,such as smart home,indoor navigation,and intelligent security.Aiming at the indoor positioning requirements of sub meter positioning accuracy,large coverage,low power consumption and low cost,this thesis studies the asynchronous TDOA(Time Difference of Array)high-precision indoor positioning model for low power wide area network(LPWAN)applications based on dual antenna base stations and the classical solution method of positioning equations.The specific research contents are as follows:(1)After investigating the main bottlenecks of existing indoor positioning technologies and positioning models in LPWAN,a high-precision indoor positioning model of asynchronous TDOA based on dual antenna base stations is proposed,and the function of the positioning model is verified on Matlab.The multi solution problem is analyzed and simulated,and the positioning model has a unique solution by making requirements for the deployment location of the base station and delimiting the positioning area.(2)The positioning accuracy of the proposed dual antenna base station positioning model is analyzed and verified by computer simulation.When the distance difference measurement error occurs,the influence of the location coordinates of the base station,the antenna feeder length,the antenna layout and the target node position on the location accuracy of the target node location coordinates is analyzed in detail,and improvement measures are proposed,and a location model that can minimize the location coordinate measurement error of the target node under the same distance difference measurement error condition is designed.(3)The realization scheme of dual antenna base station positioning model on FPGA(Field Programmable Gate Array)is designed.The positioning equations are optimized by cosine theorem.The ternary quadratic equations are sorted into the unary octave equations by Gaussian elimination method.The coordinates of the target node are calculated by Aberth+Newton iteration method,and the feasibility of implementing the algorithm on the FPGA platform is analyzed. |