Research And Design Of High Speed Spread Spectrum PLL Clock

In the multifunctional system on chip(SOC)module,the pulse peak will produce electromagnetic interference(EMI).From the perspective of spectrum,in a signal cycle,the signal spectrum almost completely overlaps with the peak spectrum of the pulse,so the EMI problem occurs.The spread frequency clock technology can suppress the energy of high-order harmonics,effectively weaken EMI,and make all kinds of equipment in the same electromagnetic environment work normally.In this thesis,a 2.4 GHz high-speed spread-spectrum PLL clock is designed.The main work includes:(1)the overall architecture is determined,and the performance index of PLL is obtained under the application background of high-speed spread spectrum clock to reduce EMI.The PLL uses Simulink to conduct behavior level modeling,establish the linear model of the module,and complete the functional verification of the system.(2)Three digital modules,adaptive frequency calibration module(AFC),Σ-Δmodulator module and lock detection module,are designed.The AFC module is based on the two-frequency search method to meet the calibration requirements of the control word in the phase-locked loop.The detection circuit helps determine the instantaneous value of the phase error and confirms that the phase-locked loop has achieved lock.(3)A third-order mash structure with phase shifting function is proposedΣ-Δmodulator,by cascading three low-order error feedback structures,migrates the quantization noise at the low frequency to the high frequency to reduce the low-frequency quantization noise,while improving theΣ-Δmodulator to increase the phase shift function to adjust the phase of the phase-locked loop.(4)A cross coupled oscillator based on LC is designed.The oscillator circuit uses a temperature compensation structure,and the switch capacitor and variable capacitor are used for coarse and fine adjustment.The continuity of frequency coverage is ensured by changing the variable capacitor value of temperature compensation.(5)A TSPC 4/5prescaler is designed,which is composed of three TSPC DFFs and mode control logic.Compared with the traditional structure,it can reduce the power loss.The phase-locked loop designed in this thesis uses SMIC 55nm IP6M CMOS process,and the whole phase-locked loop is simulated and verified on tape.When the power supply voltage is 1.2 V,the clock input frequency is 20 MHz,the duty cycle of the clock input square wave is 50%,the locking time is less than 50μs,the phase noise at 1 MHz frequency offset is-110 d Bc/Hz,the PLL chip area is 0.37 mm~2,and the actual output frequency is 2.3 GHz～3.2 GHz.