Design Of Cascaded Digital Decimation Filter In Sigma-Delta ADC

In today’s world,with the booming development of digital communication and IC design,more and more research is focused on Sigma-Delta ADC,which are constantly moving towards high performance and low power consumption.And it is in this context that this paper conducts market research on audio chips and designs an audio chip based on cascaded digital decimation filters with the Sigma-Delta algorithm as the core and with the help of IC design platforms,through the processes of requirements analysis,product creation,system modelling,circuit design and layout implementation.The audio chip designed in this article takes Sigma-Delta ADC as the research core and the digital decimation filter in Sigma-Delta ADC as the research object.Based on the third-order CIFF(Cascade of Integrators Feed Forward)structure of the Sigma-Delta modulator,a cascaded digital decimation filter is designed to meet the performance indicators of signal-to-noise ratio not less than 120d B and effective bits not less than 20 bits.After type selection and structural comparison,the digital extraction filter ultimately adopts a three-level cascade structure.The first stage is composed of a 4-order CIC filter,the second stage is a 51-order FIR compensation filter,and the third stage is a 70-order half band filter.During the design,system modeling and structural improvement were carried out,and a recursive structure was used to optimize the structure of the CIC filter;Using multiphase decomposition technology to optimize the model of FIR compensation filters and half band filters;Using coefficient symmetry technology and CSD encoding technology to optimize the coefficients of the multiplier.After optimization,approximately 50%of the multiplier and 13%of the adder units were reduced,reducing the overall computational load and complexity.After multi-level and multi-angle optimization,the layout area of the final digital extraction filter has been reduced by about 15%,and the logical resource utilization has been reduced by about 23%.After the cascade model of the digital decimation filter has been designed and validated,the layout area of the digital decimation filter is about 0.11mm~2,and the power consumption of the digital circuit is about 3.9m W.based on this,chip casting is carried out using SMIC 0.188)CMOS technology.Finally,the chip was tested,and the signal-to-noise ratio of Sigma-Delta ADC was 122.3d B,the validity digit indicator was 20 bits,and the chip power consumption was 6.12m W.After testing,all indicators meet the design requirements,so this design ultimately successfully developed a digital decimation filter.