Research On Efficient Decoding Algorithms For Polar Codes

Channel coding is one of the most important technologies in the wireless communication systems.Polar codes,as the only coding scheme that are therotically proven to achieve the channel capacity,have become one of the most promising research directions.However,there are two main drawbacks associated with the polar decoding algorithms.First,the popular successive cancellation list(SCL)decoding falls short in providing a reasonable error-correction performance for practical moderate code lengths and list size.Second,the sequential bit-by-bit nature of SC-based decoding leads to high decoding latency and low throughput in terms of hardware implementation,which hinders its application in low-latency communication senarios.Therefore,it is meaningful to investigate high-efficiency and low-latency decoding algorithms for polar codes under ultra-reliable and low-latency communication senarios.Aiming at tackling the aforementioned issues,this thesis develops efficient decoding algorithms for polar codes.First,aiming at improving the decoding performance of SCL decoder,this paper focus on advancing the framework of dynamic bit-flipping strategy to make it feasible for the SCL decoder.The principle of bit-flipping is to flip the decoding output in additional re-decoding attempts in case the initial decoding fails.A flipping metric from the path metric(PM)domain is obtained to determine the bit positions that are more prone to decoding errors.The proposed flipping metric is then combined with the dynamic bit-flipping strategy to devise a new decoder,referred to as the dynamic SCL-Flip(D-SCL-Flip)decoder,which dynamically builds a set of candidate flipping bits based on the proposed flipping metric,such that the new decoding attempts are performed by adopting the flipping bits that has the highest probability of correcting the decoding errors.Simulation results show that the proposed D-SCL-Flip decoder is able to outperform the state-of-the-art,by providing better error-correcting performance(0.1 d B)yet with fewer re-decoding attempts(34.6%).Furthermore,for ease of practical implementation,several simplifications on different aspects of the D-SCL-Flip decoder are presented,including the calculation of the flipping metric,deep learning(DL)aided decoding,and fast decoding techniques.All these simplifications are shown to have minimal impact on the error-correcting performance,while much lower computational complexity and decoding latency are permitted.Second,since the sequential nature of the SC algorithm leads to significant decoding latencies,this paper propose fast SC decoding algorithms by implementing parallel decoders at the intermediate levels of the SC decoding tree for some special nodes with specific information and frozen bit patterns,such that SC decoding process can be accelerated.First,this paper present a new class of special nodes composed of a sequence of rate one or single-parity-check(SR1/SPC)nodes,which can be easily found especially in high-rate polar code and is able to envelop a wide variety of existing special node types.Then,the parity constraints caused by the frozen bits in each descendant node are analysed.Based on these parity constraints,a generalized fast decoding algorithm is proposed to decode SR1/SPC nodes efficiently,such that the parallelism of SC decoding is further improved.Simulation results show that the proposed decoding algorithm of the SR1/SPC node can achieve near-maximum-likelihood(ML)performance,and the overall decoding latency can be significantly reduced by 43.8%,as compared to the state-of-the-art fast SC decoder.