Structural Design And Interface Control Of High-κ Gate Dielectric InP MOS Device

Metal oxide semiconductor（MOS）capacitors are used in many applications such as optoelectronics,microelectronics,and biomedical diagnostics because of their excellent optical and electrical properties.However,as the integration of integrated circuits has increased,metal oxide semiconductor field effect transistors（MOSFETs）feature sizes are required to be reduced to less than 1 nm.This has led to a dramatic deterioration in the performance of Si O₂gate dielectric MOSFETs.The huge leakage current causes a sharp increase in the static power consumption of logic circuits,as well as high-frequency dispersion,poor reliability,and increased errors.Direct electron tunneling of Si O₂films with thickness less than 1 nm has been reported to lead to severe leakage currents.Therefore,high-κgate dielectrics have been sought to replace Si O₂,increase the physical thickness and reduce the leakage current.Er₂O₃,as a typical rare earth oxide,is one of the most promising gate dielectrics to replace Si O₂because of its large band gap（5.8 e V）,large valence band shift（3.5 e V）,and suitable highκvalue.Silicon-based semiconductors can no longer meet the current requirements of the IC industry for high mobility and low power consumption,so it is of great academic and practical importance to select new high mobility III-V semiconductor materials for integration with highκgate dielectrics.The prepared MOS devices can solve the key problems of high leakage current,high power consumption and low speed,which can further enable the IC technology to continue to develop along Moore’s law.However,the large surface activity of III-V semiconductor materials tends to form surface defects,which limits the operational performance of the devices.Therefore,obtaining high-quality Er₂O₃thin films and tuning the density of interfacial states between the gate dielectric layer and the substrate material become a major challenge to drive the CMOS device process advancement.This thesis explores the preparation process,interface regulation and device performance enhancement of Er₂O₃thin films around these key scientific issues.The specific research and results of this thesis are as follows:（1）The effects of atomic layer deposition（ALD）-derived Al₂O₃passivation layer and annealing temperature on the interfacial chemistry and transport properties of Er₂O₃high-κgate dielectrics sputter-deposited on Si substrates were systematically investigated.X-ray photoelectron spectroscopy（XPS）analysis showed that the ALD-derived alumina passivation layer significantly prevented the appearance of low-κhydroxides generated by moisture absorption of the gate oxide and greatly optimized the gate dielectric properties.Electrical measurements show that the Al₂O₃/Er₂O₃/Si gate stack structure annealed at 450°C has excellent dielectric properties with a leakage current density of 1.38×10^-9A/cm²at an applied voltage of 1 V.As a complement,the leakage current conduction mechanism of MOS capacitors under different stack structures is systematically investigated.（2）Ultrathin Hf O₂,Al₂O₃,Hf Al O passivation layers were prepared based on ALD technology,and three stacking structures（Er₂O₃/Hf O₂/In P,Er₂O₃/Al₂O₃/In P,Er₂O₃/Hf Al O/In P）were constructed to study the effects of different kinds of passivation layers on the interface and electrical properties of In P-MOS devices.The results show that the Hf Al O passivation layer can effectively reduce the interface density of state(D_it)and improve the electrical performance of the device,and the D_itcan be reduced from 3.53×10¹³cm^-2to4.81×10¹²cm^-2,compared with other passivation layers,the dielectric constant is increased from 7.7 to 23.8,and the leakage current density is decreased from 2.95×10^-9A/cm²to 1.67×10^-10A/cm².The MOS devices with high performance and low gate leakage current are obtained.