Design And Application Of Error Correction Unit Of NAND Flash Test System Based On FPGA

At present,NAND Flash,which has the advantages of non-volatility,low energy consumption and high-speed data storage,has been widely used in various portable electronic products and various types of digital devices.With the optimization of NAND Flash storage capacity and cost,large-capacity 3D MLC structure NAND Flash is facing severe challenges in terms of data reliability.In order to alleviate the reliability problems caused by the structure and technology of NAND Flash,LDPC codes with good error correction performance have replaced BCH codes and Hamming codes and become the mainstream codec scheme for flash memory data storage.At the same time,it is particularly important to test the reliability of flash memory data.At present,the ATE integrates the LDPC ECC module through the hardware to correct the data to improve the accuracy and efficiency of the test,and can better guarantee the quality and stability of the test.However,in the face of the huge amount of test data in the 3D MLC NAND Flash batch test,repetitive reading and writing traversal,and the increase in the reading delay of the test system under the LDPC algorithm reading mechanism,how to reduce the time for data reliability testing Consumption problem is an important research direction of flash memory testing at present.At present,the research on LDPC algorithm in flash memory test mainly focuses on acceleration and resource optimization from the perspective of ECC hardware implementation.In this paper,the reading performance of flash memory test is improved from the aspects of algorithm decoding delay and data refresh delay,and the LDPC algorithm is implemented through the FPGA hardware platform.The design of the error correction unit verifies the feasibility and effectiveness of the algorithm through the actual flash memory test results.(1)Aiming at the problem of LDPC decoding delay caused by different retention times and erasure times,this paper proposes an LDPC sensing voltage application scheme under different error types.This solution first equalizes the voltage offset and overlapping problems caused by storage time and inter-unit interference in the flash memory,so as to alleviate the complicated problems of the subsequent LDPC decoding process.Then apply the corresponding induction voltage according to the degree of different error types of the flash memory to reduce the delay of induction and transmission.The simulation results show that the reading delay of the low page and high page of NAND Flash is decreased by 27.8% and 23% respectively.(2)Aiming at the reduction of flash memory performance and lifespan caused by frequent refresh of flash memory,this paper improves a remapping refresh technology(RLR),which reduces the refresh cost by remapping the enhanced ECC parity bit,and double aggregation in Delaunay Based on the identification of similar hot data,through this remapping refresh scheme,different refresh strategies(AR-RLR)are adopted for accurate data and approximate data.The simulation results show that the read delay is reduced by 30.8%.(3)This paper uses the proposed LDPC multi-voltage sensing method based on error types to design the NAND Flash error correction unit on the FPGA hardware platform.The test results of the flash memory also verify the feasibility and effectiveness of the algorithm.